RF65 Datasheet, PDF (20/72 Pages) List of Unclassifed Manufacturers – Low Power Integrated UHF Receiver With -120dBm High Sensitivity

ADVANCED COMMUNICATIONS & SENSING
RF65
DATASHEET
3.4.4. Continuous-Time DAGC
In addition to the automatic gain control described in section 3.4.3, the RF65 is capable of continuously adjusting its gain in
the digital domain, after the analog to digital conversion has occured. This feature, named DAGC, is fully transparent to the
end user. The digital gain adjustment is repeated every 2 bits, and has the following benefits:
 Fully transparent to the end user
 Improves the fading margin of the receiver during the reception of a packet, even if the gain of the LNA is frozen
 Improves the receiver robustness in fast fading signal conditions, by quickly adjusting the receiver gain (every 2 bits)
 Works in Continuous, Packet, and unlimited length Packet modes
The DAGC is enabled by setting RegTestDagc to 0x10 for low modulation index systems (i.e. when AfcLowBetaOn=1,
refer to section 3.4.17), and 0x30 for other systems. See section 9.5 for details. It is recommended to always enable the
DAGC.
3.4.5. Quadrature Mixer - ADCs - Decimators
The mixer is inserted between output of the RF buffer stage and the input of the analog to digital converter (ADC) of the
receiver section. This block is designed to translate the spectrum of the input RF signal to base-band, and offer both high
IIP2 and IIP3 responses.
In the lower bands of operation (290 to 510 MHz), the multi-phase mixing architecture with weighted phases improves the
rejection of the LO harmonics in receiver mode, hence increasing the receiver immunity to out-of-band interferers.
The I and Q digitalization is made by two 5^th order continuous-time Sigma-Delta Analog to Digital Converters (ADC). Their
gain is not constant over temperature, but the whole receiver is calibrated before reception, so that this inaccuracy has no
impact on the RSSI precision. The ADC output is one bit per channel. It needs to be decimated and filtered afterwards. This
ADC can also be used for temperature measurement, please refer to section 3.4.18 for more details.
The decimators decrease the sample rate of the incoming signal in order to optimize the area and power consumption of
the following receiver blocks.
3.4.6. Channel Filter
The role of the channel filter is to filter out the noise and interferers outside of the channel. Channel filtering on the RF65 is
implemented with a 16-tap Finite Impulse Response (FIR) filter, providing an outstanding Adjacent Channel Rejection
performance, even for narrowband applications.
Note to respect oversampling rules in the decimation chain of the receiver, the Bit Rate cannot be set at a higher value
than 2 times the single-side receiver bandwidth (BitRate < 2 x RxBw)
The single-side channel filter bandwidth RxBw is controlled by the parameters RxBwMant and RxBwExp in RegRxBw:
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