RF65 Datasheet, PDF (42/72 Pages) List of Unclassifed Manufacturers – Low Power Integrated UHF Receiver With -120dBm High Sensitivity

ADVANCED COMMUNICATIONS & SENSING
RF65
DATASHEET
5.3. Digital IO Pins Mapping
Six general purpose IO pins are available on the RF65, and their configuration in Continuous or Packet mode is
controlled through RegDioMapping1 and RegDioMapping2.
5.3.1. DIO Pins Mapping in Continuous Mode
Table 17 DIO Mapping, Continuous Mode
Mode
Sleep
Stdby
FS
Rx
Diox
Mapping
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
DIO5
-
-
LowBat
ModeReady
ClkOut
-
LowBat
ModeReady
ClkOut
-
LowBat
ModeReady
ClkOut
Rssi
LowBat
ModeReady
DIO4
-
-
LowBat
-
-
-
LowBat
-
-
-
LowBat
PllLock
Timeout
RxReady
SyncAddress
PllLock
DIO3
-
-
AutoMode
-
-
-
AutoMode
-
-
-
AutoMode
-
Rssi
RxReady
AutoMode
Timeout
DIO2
-
-
-
-
-
-
-
-
-
-
-
-
Data
Data
Data
Data
DIO1
DIO0
-
-
LowBat
-
-
-
LowBat
-
-
-
LowBat
PllLock
Dclk
RxReady
LowBat
SyncAddress
-
-
LowBat
ModeReady
-
-
LowBat
ModeReady
PllLock
-
LowBat
ModeReady
SyncAddress
Timeout
Rssi
ModeReady
5.3.2. DIO Pins Mapping in Packet Mode
Table 18 DIO Mapping, Packet Mode
Mode
Sleep
Stdby
FS
Rx
Diox
Mapping
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
DIO5
-
-
LowBat
ModeReady
ClkOut
-
LowBat
ModeReady
ClkOut
-
LowBat
ModeReady
ClkOut
Data
LowBat
ModeReady
DIO4
-
-
LowBat
-
-
-
LowBat
-
-
-
LowBat
PllLock
Timeout
Rssi
RxReady
PllLock
DIO3
DIO2
DIO1
DIO0
FifoFull
-
LowBat
-
FifoFull
-
LowBat
-
FifoFull
-
LowBat
PllLock
FifoFull
Rssi
SyncAddress
PllLock
FifoNotEmpty
-
LowBat
AutoMode
FifoNotEmpty
-
LowBat
AutoMode
FifoNotEmpty
-
LowBat
AutoMode
FifoNotEmpty
Data
LowBat
AutoMode
FifoLevel
FifoFull
FifoNotEmpty
-
FifoLevel
FifoFull
FifoNotEmpty
-
FifoLevel
FifoFull
FifoNotEmpty
PllLock
FifoLevel
FifoFull
FifoNotEmpty
Timeout
-
-
LowBat
-
-
-
LowBat
-
-
-
LowBat
PllLock
CrcOk
PayloadReady
SyncAddress
Rssi
Note Received Data is only shown on the Data signal between RxReady and PayloadReady’s rising edges
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