NUC920ABN Datasheet, PDF (490/529 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC920ABN
32-BIT ARM926EJ-S BASED MCU
PS2 Host Controller Status Register (PS2STS)
Register
PS2STS
Address
0xB800_9004
0xB800_9104
R/W Description
R/W Status register
31
30
23
22
15
14
7
6
RESERVED
29
21
13
5
Tx_err
28
27
26
RESERVED
20
19
18
RESERVED
12
11
10
RESERVED
4
3
2
Tx_IRQ
RESERVED
Reset Value
0x0000_0000
25
17
9
1
Rx_2bytes
24
16
8
0
Rx_IRQ
Bits
[5]
[4]
[1]
[0]
Descriptions
Tx_err
Tx_IRQ
Rx_2bytes
Rx_IRQ
Transmit Error Status
This bit indicates software that device doesn’t response ACK after Host wrote
a command to it.
This bit is valid when Tx_IRQ is asserted. It will automatically reset after
software starts next command writing process. If software writes one to this
bit, it also can be clear.
Transmit Complete Interrupt
This bit indicates software that the process of Host controller writing command
to device is finished. Software needs to write one to this bit to clear this
interrupt.
Receive 2 Bytes Flag
This bit indicates software that Host controller receives two byte data from
device. The second data are stored at the high byte of PS2_SCANCODE
register. This bit is valid when Rx_IRQ is asserted, and is read only.
Receive Interrupt
This bit indicates software that Host controller receives one byte data from
device. This data is stored at PS2_SCANCODE register. Software needs to
write one to this bit to clear this interrupt after reading receiving data in
Rx_SCAN_CODE register.
Publication Release Date: Jun. 18, 2010
490
Revision: A3