NUC920ABN Datasheet, PDF (350/529 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC920ABN
32-BIT ARM926EJ-S BASED MCU
Interrupt Control and Status Register (INTR)
Register
INTR
Offset
0xB000_A004
R/W Description
R/W Interrupt Control and Status Register
Reset Value
0x0000_0000
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
Reserved
15
14
13
12
11
10
9
8
Reserved
DTA_IF EOS_IF DMARQ_IF INTRQ_IF
7
6
5
4
3
2
1
0
Reserved
DTA_IE EOS_IE DMARQ_IE INTRQ_IE
Bits
[11]
[10]
[9]
[8]
Descriptions
DTA_IF
EOS_IF
DMARQ_IF
INTRQ_IF
DMAC READ/WRITE Target Abort Interrupt Flag
This bit indicates DMAC received an ERROR response from internal AHB bus
during DMA read/write operation.
0 = No bus ERROR response received.
1 = Bus ERROR response received.
NOTE: This bit is read only, but can be cleared by writing ‘1’ to it.
End of Sectors Transfer Interrupt Flag
0 = End of sectors condition did not occur.
1 = End of sectors condition occurred.
NOTE: This bit is read only, but can be cleared by writing ‘1’ to it.
DMARQ Interrupt Flag
0 = No DMARQ assertion/negation is detected.
1 = DMARQ assertion/negation is detected.
NOTE: This bit is read only, but can be cleared by writing ‘1’ to it. If the
DMARQ_IF is cleared by writing ‘1’ to it, while the DMARQ line is still
asserted or negated; this bit remains ‘0’ until a new assertion/negation is
detected on DMARQ line.
INTRQ Interrupt Flag
0 = No INTRQ assertion is detected.
1 = INTRQ assertion is detected.
NOTE: This bit is read only, but can be cleared by writing ‘1’ to it. If the
INTRQ_IF is cleared by writing ‘1’ to it, while the INTRQ line is still asserted;
Publication Release Date: Jun. 18, 2010
350
Revision: A3