NUC920ABN Datasheet, PDF (128/529 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC920ABN
32-BIT ARM926EJ-S BASED MCU
MII Management Control and Address Register (MIIDA)
The EMC provides MII management function to access the control and status registers of the external PHY.
The MIIDA register is used to keep the MII management command information, like the register address,
external PHY address, MDC clocking rate, read/write etc.
Register
MIIDA
Address
0xB000_3098
R/W Description
R/W ^{MII Management Control and Address Register}
Reset Value
0x0090_0000
31
30
29
23
22
21
MDCCR
15
14
13
Reserved
7
6
5
Reserved
28
27
Reserved
20
19
MDCON
12
11
4
3
26
18
PreSP
10
PHYAD
2
PHYRAD
25
17
BUSY
9
1
24
16
Write
8
0
Bits
[23:20]
Descriptions
MDCCR
MDC Clock Rating
Default Value: 4’h9
The MDCCR controls the MDC clock rating for MII Management I/F.
Depend on the IEEE Std. 802.3 clause 22.2.2.11, the minimum period for
MDC shall be 400ns. In other words, the maximum frequency for MDC is
2.5MHz. The MDC is divided from the AHB bus clock, the HCLK.
Consequently, for different HCLKs the different ratios are required to
generate appropriate MDC clock. The T_HCLK indicates the period of HCLK.
MDCCR
MDC Clock Period MDC Clock Frequency
[23:20]
4’b0000
4’b0001
4’b0010
4’b0011
4’b0100
4’b0101
4’b0110
4’b0111
4’b1000
4’b1001
4’b1010
4’b1011
4’b1100
4’b1101
4’b1110
4’b1111
4 x T_HCLK
6 x T_HCLK
8 x T_HCLK
12 x T_HCLK
16 x T_HCLK
20 x T_HCLK
24 x T_HCLK
28 x T_HCLK
30 x T_HCLK
32 x T_HCLK
36 x T_HCLK
40 x T_HCLK
44 x T_HCLK
48 x T_HCLK
54 x T_HCLK
60 x T_HCLK
HCLK/4
HCLK/6
HCLK/8
HCLK/12
HCLK/16
HCLK/20
HCLK/24
HCLK/28
HCLK/30
HCLK/32
HCLK/36
HCLK/40
HCLK/44
HCLK/48
HCLK/54
HCLK/60
Publication Release Date: Jun. 18, 2010
128
Revision: A3