NUC920ABN Datasheet, PDF (362/529 Pages) Nuvoton Technology Corporation – 32-BIT ARM926EJ-S BASED MCU

NUC920ABN
32-BIT ARM926EJ-S BASED MCU
UDMA Transfer Timing Control Register (UDMATTR)
Register
UDMATTR
Offset
0xB000_A02C
R/W
R/W
Description
UDMA Transfer Timing Control Register
Reset Value
0x0002_0206
31
30
29
28
27
26
25
24
Reserved
23
22
21
20
19
18
17
16
UDMAtCYC
15
14
13
12
11
10
9
8
UDMAtDVS
7
6
5
4
3
2
1
0
UDMAtRP
Bits
Descriptions
[23:16] UDMAtCYC
UDMA Transfer Timing Parameter tCYC
tCYC, cycle time of HSTROBE.
( The actual cycle time will be [clock period*(UDMAtCYC+2)] )
[15:8]
UDMAtDVS
UDMA Transfer Timing Parameter tDVS
tDVS, data valid setup time at sender.
( The actual setup time will be [clock period*(UDMAtDVS+1)] )
[7:0]
UDMAtRP
UDMA Transfer Timing Parameter tRP
tRP, time period between HDMARDY- negation and STOP assertion during
host terminating an Ultra DMA data-in burst.
NOTE: Unit of these values is in engine clock cycles. UDMAtDVS should be never greater than UDMAtCYC.
HSTROBE
UDMAtCYC
UDMAtCYC
DD[15:0]
UDMAtDVS
Sustained Ultra DMA data-out burst
Suggest Value (@66MHz)
UDMAtCYC
UDMAtDVS
Mode 0
6
4
Mode 1
4
3
Mode 2
2
2
Mode 3
1
1
Mode 4
0
0
Publication Release Date: Jun. 18, 2010
362
Revision: A3