GMS81504 Datasheet, PDF (39/54 Pages) List of Unclassifed Manufacturers – CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

HYUNDAI MicroElectronics
GMS81504
BRK Interrupt
Software interrupt can be invoked by BRK instruction,
which is the lowest priority order.
Interrupt vector address of BRK is shared with the
vector of TCALL0 (Refer to Program Memory Sec-
tion). When BRK interrupt is generated, B-flag of
PSW is set to distinguish BRK from TCALL0.
Each processing step is determined by B-flag as shown
below.
Multiple Interrupt
If two requests of different priority levels are received
simultaneously, the request of higher priority level is
serviced. If requests of the same priority level are
received simultaneously, an internal polling sequence
determines by hardware which request is serviced.
Hardware interrupt priority is shown in Page36.
However, multiple processing through software for
special features is possible. Generally when an inter-
rupt is accepted, the I-flag is cleared to disable any
further interrupt. But as user set I-flag in interrupt
routine, some further interrupt can be serviced even if
certain interrupt is in progress.
BRK or
TCALL0
B-FLAG ^{= 0}
=1
BRK
INTERRUPT
ROUTINE
TCALL0
ROUTINE
RETI
RET
Figure 31. Execution of BRK/ TCALL0
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER 0 is in progress.
Because of re-setting the interrupt enable registers IENH, IENL
and master enable flag "EI" in the Timer/Counter 0 routine.
MAIN
ROUTINE
TIMER 0
ROUTINE
MOV IENH,#80H
MOV IENL,#00H
EI
INT 0
ROUTINE
Occur
TIMER 0 INTERRUPT
INT0
ROUTINE
MOV IENH,#FFH
MOV IENL,#FFH
RETI
RETI
Figure 32. Execution of Multi-Interrupt
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