GMS81504 Datasheet, PDF (36/54 Pages) List of Unclassifed Manufacturers – CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER

GMS81504
HYUNDAI MicroElectronics
INTERRUPTS
The GMS81504 interrupt circuits consist of Interrupt
enable register (IENH, IENL), Interrupt request flags
of IRQH, IRQL, priority circuit and Master enable
flag(I flag of PSW). The configuration of interrupt
circuit is shown in Figure 1-26.
12 interrupt sources are provided including the Reset.
Interrupt source
Symbol Priority
Hardware RESET
RESET
1
External Interrupt 0
INT0IF
2
External Interrupt 1
INT1IF
3
Timer/Counter 0
T0IF
4
Timer/Counter 1
T1IF
5
AD Converter
AIF
6
Basic interval timer
BITIF
7
*Vector addresses are shown in Program Memory
section.
The External Interrupts INT0, INT1 can each be tran-
sition-activated, depending on interrupt edge selection
register.
The Timer 0, Timer 1 Interrupts are generated by T0IF,
T1IF, which are set by a match in their respective
timer/counter register.
The AD converter Interrupt is generated by AIF which
is set by finishing the analog to digital conversion.
The Basic Interval Timer Interrupt is generated by
BITIF which are set by a overflow in the timer/counter
register.
The interrupts are controlled by the interrupt master
enable flag I-flag (bit 2 of PSW), the interrupt enable
register (IENH, IENL) and the interrupt request flags
(in IRQH, IRQL) except Power-on reset and software
BRK interrupt.
Interrupt enable registers are shown in Figure 27.
These registers are composed of interrupt enable flags
of each interrupt source, these flags determines
whether an interrupt will be accepted or not. When
enable flag is "0", a corresponding interrupt source is
prohibited. Note that PSW contains also a master en-
able bit, I-flag, which disables all interrupts at once.
INTERRUPT REQUEST FLAG
INTERRUPT ENABLE FLAG
INT0
INT1
TIMER0
TIMER1
IRQH
IENH
INT0IF ^{BIT 7}
0
1
INT1IF ^{BIT 6}
T0IF ^{BIT 3}
T1IF ^{BIT 2}
ADC
BIT *
IRQL
IENL
BIT 7
AIF
BIT 5
BITIF
PRIORITY
CONTROL
I-flag is in PSW, it is cleared by "DI", set by "EI"
instruction.
When it goes interrupt service, I-flag is cleared by
hardware, thus any other interrupt are inhibited.
When interrupt service is completed by "RETI"
instruction, I-flag is set to "1" by hardware.
BRK (Software Interrupt)
0
1
I-FLAG
Master Interrupt
Enable Flag
RELEASE THE STOP
(IF IN STOP MODE)
TO CPU
RESET
NOTE:
* BIT: BASIC INTERVAL TIMER
Figure 1-26. Block Diagram of Interrupt Function
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