M052LDN Datasheet, PDF (37/86 Pages) List of Unclassifed Manufacturers – 32-bit Microcontroller

M051 DN/DE
6.3.2 System Clock and SysTick Clock
The system clock has 4 clock sources which were generated from clock generator block. The
clock source switch depends on the register HCLK_S (CLKSEL0[2:0]). The block diagram is
shown below.
HCLK_S (CLKSEL0[2:0])
22.1184 MHz
HIRC
111
10 kHz LIRC
011
PLL FOUT
010
Reserved
001
4~24 MHz HXT
000
1/(HCLK_N+1)
HCLK_N (CLKDIV[3:0])
CPUCLK
HCLK
PCLK
CPU
AHB
APB
CPU in Power Down Mode
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 6-6 System Clock Block Diagram
The clock source of SysTick in Cortex-M0 core can use CPU clock or external clock
(SYST_CSR[2]). If using external clock, the SysTick clock (STCLK) has 4 clock sources. The
clock source switch depends on the setting of the register STCLK_S (CLKSEL0[5:3]. The block
diagram is shown below.
22.1184 MHz
HIRC
1/2
HCLK
1/2
4~24 MHz HXT
1/2
Reserved
4~24 MHz HXT
STCLK_S (CLKSEL0[5:3])
111
011
010
STCLK
001
000
Legend:
HXT = 4~24 MHz external high speed crystal oscillator
HIRC = 22.1184 MHz internal high speed RC oscillator
LIRC = 10 kHz internal low speed RC oscillator
Note: Before clock switching, both the pre-selected and newly selected clock sources must be
turned on and stable.
Figure 6-7 SysTick clock Control Block Diagram
Oct. 05, 2015
Page 37 of 86
Rev 1.03