M052LDN Datasheet, PDF (25/86 Pages) List of Unclassifed Manufacturers – 32-bit Microcontroller

M051 DN/DE
6.2 System Manager
6.2.1 Overview
System management includes the following sections:
 System Resets
 System Power Architecture
 System Memory Map
 System management registers for Part Number ID, chip reset and on-chip controllers
reset, and multi-functional pin control
 System Timer (SysTick)
 Nested Vectored Interrupt Controller (NVIC)
 System Control registers
6.2.2 System Reset
The system reset can be issued by one of the following listed events. For these reset event flags
can be read by RSTSRC register.
 Hardware Reset
 Power-on Reset (POR)
 Low level on the Reset Pin (nRST)
 Watchdog Timer Time-out Reset (WDT)
 Low Voltage Reset (LVR)
 Brown-out Detector Reset (BOD)
 Software Reset
 MCU Reset - SYSRESETREQ(AIRCR[2])
 Cortex^® -M0 Core One-shot Reset - CPU_RST(IPRSTC1[1])
 Chip One-shot Reset - CHIP_RST(IPRSTC1[0])
Note: ISPCON.BS keeps the original value after MCU Reset and CPU Reset.
Oct. 05, 2015
Page 25 of 86
Rev 1.03