M052LDN Datasheet, PDF (33/86 Pages) List of Unclassifed Manufacturers – 32-bit Microcontroller

M051 DN/DE
42
43
44
45
46-47
0xA8
0xAC
0xB0
0xB4
0xB8-0xBC
26
27
28
29
30-31
ACMP23_INT
ACMP2/3
Analog Comparator 2 or Comparator
3 interrupt
Yes
Reserved
PWRWU_INT CLKC
Clock controller interrupt for chip
wake-up from Power-down state
Yes
ADC_INT
ADC
ADC interrupt
No
Reserved
-
-
Table 6-3 System Interrupt Map Vector Table
6.2.7.2 Vector Table
When an interrupt is accepted, the processor will automatically fetch the starting address of the
interrupt service routine (ISR) from a vector table in memory. For ARMv6-M, the vector table base
address is fixed at 0x00000000. The vector table contains the initialization value for the stack
pointer on reset, and the entry point addresses for all exception handlers. The vector number on
previous page defines the order of entries in the vector table associated with exception handler
entry as illustrated in previous section.
Vector Table Word Offset
0
Vector Number
Description
SP_main – The Main stack pointer
Exception Entry Pointer using that Vector Number
Table 6-4 Vector Figure Format
6.2.7.3 Operation Description
NVIC interrupts can be enabled and disabled by writing to their corresponding Interrupt Set-
Enable or Interrupt Clear-Enable register bit-field. The registers use a write-1-to-enable and write-
1-to-clear policy, both registers reading back the current enabled state of the corresponding
interrupts. When an interrupt is disabled, interrupt assertion will cause the interrupt to become
Pending, however, the interrupt will not be activated. If an interrupt is Active when it is disabled, it
remains in its Active state until cleared by reset or an exception return. Clearing the enable bit
prevents new activations of the associated interrupt.
NVIC interrupts can be pended/un-pended using a complementary pair of registers to those used
to enable/disable the interrupts, named the Set-Pending Register and Clear-Pending Register
respectively. The registers use a write-1-to-enable and write-1-to-clear policy, both registers
reading back the current pended state of the corresponding interrupts. The Clear-Pending
Register has no effect on the execution status of an Active interrupt.
NVIC interrupts are prioritized by updating an 8-bit field within a 32-bit register (each register
supporting four interrupts).
The general registers associated with the NVIC are all accessible from a block of memory in the
System Control Space and will be described in next section.
Oct. 05, 2015
Page 33 of 86
Rev 1.03