RFM24W Datasheet, PDF (28/34 Pages) List of Unclassifed Manufacturers – ISM Transceiver module

RFM24W
6. Data Handling and Packet Handler
6.1. RX and TX FIFOs
Two 64 byte FIFOs are integrated into the chip, one for RX and one for TX, as shown in Figure 11. Writing to
command register 66h will load data into the TX FIFO and reading from command register 77h will read data from
the RX FIFO. The TX FIFO has a threshold for when the FIFO is almost empty which is set by the
“TX_FIFO_EMPTY” property. An interrupt event occurs when the data in the TX FIFO reaches the almost empty
threshold. If more data is not loaded into the FIFO then the chip automatically exits the TX State after the ipksent
interrupt occurs. The RX FIFO has one programmable threshold which is programmed by setting the
“RX_FIFO_FULL” property. When the incoming RX data crosses the Almost Full Threshold an interrupt will be
generated to the microcontroller via the nIRQ pin. The microcontroller will then need to read the data from the RX
FIFO. Both the TX and RX FIFOs may be cleared or reset with the “FIFO_RESET” command.
TX FIFO
RX FIFO
RX FIFO Almost
Full Threshold
TX FIFO Almost
Empty Threshold
Figure 11. TX and RX FIFOs
6.2. Packet Handler
When using the FIFOs, automatic packet handling may be enabled for TX mode, RX mode, or both. The usual fields
for network communication (such as preamble, synchronization word, headers, packet length, and CRC) can be
configured to be automatically added to the data payload. The fields needed for packet generation normally change
infrequently and can therefore be stored in registers. Automatically adding these fields to the data payload in TX
mode and automatically checking them in RX mode greatly reduces the amount of communication between the
microcontroller and Si446x. It also greatly reduces the required computational power of the microcontroller. The
general packet structure is shown in Figure 12. Any or all of the fields can be enabled and checked by the internal
packet handler. The Header/Frame/Length section is entirely configurable to almost any packet configuration with
the match/value configuration properties. Reference designs and examples are available for 15.4g and MBUS
packet structures.
Preamble
Sync
Header /
Frame/
Length
Payload
Figure 12. Packet Handler Structure
CRC
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