RFM24W Datasheet, PDF (23/34 Pages) List of Unclassifed Manufacturers – ISM Transceiver module

RFM24W
4.2.1. FIFO Mode
In FIFO mode, the transmit and receive data is stored in integrated FIFO register memory. The TX FIFO is
accessed by writing command 66h followed directly by the data/clk that the host wants to write into the TX FIFO.
The RX FIFO is accessed by writing command 77h followed by the number of clock cycles of data the host would
like to read out of the RX FIFO. The RX data will be clocked out onto the SDO pin.
In TX mode if the packet handler is enabled, the data bytes stored in FIFO memory are "packaged" together with
other fields and bytes of information to construct the final transmit packet structure. These other potential fields
include the Preamble, Sync word, Header, CRC checksum, etc. The configuration of the packet structure in TX
mode is determined by the Automatic Packet Handler (if enabled), in conjunction with a variety of Packet Handler
properties. If the Automatic Packet Handler is disabled, the entire desired packet structure should be loaded into
FIFO memory; no other fields (such as Preamble or Sync word will be automatically added to the bytes stored in
FIFO memory). For further information on the configuration of the FIFOs for a specific application or packet size,
see "6. Data Handling and Packet Handler" on page 29. In RX mode, only the bytes of the received packet
structure that are considered to be "data bytes" are stored in FIFO memory. Which bytes of the received packet are
considered "data bytes" is determined by the Automatic Packet Handler (if enabled), in conjunction with the Packet
Handler configuration. If the Automatic Packet Handler is disabled, all bytes following the Sync word are
considered data bytes and are stored in FIFO memory. Thus, even if Automatic Packet Handling operation is not
desired, the preamble detection threshold and Sync word still need to be programmed so that the RX Modem
knows when to start filling data into the FIFO. When the FIFO is being used in RX mode, all of the received data
may still be observed directly (in realtime) by properly programming a GPIO pin as the RXDATA output pin; this can
be quite useful during application development. When in FIFO mode, the chip will automatically exit the TX or RX
State when either the ipksent or ipkvalid interrupt occurs. The chip will return to the IDLE state programmed in the
argument of the “START TX” or “START RX” API command, TXCOMPLETE_STATE[3:0] or
RXCOMPLETE_STATE[3:0]. For example, the chip may be placed into TX mode by sending the “START TX”
command and by writing the 30h to the TXCOMPLETE_STATE[3:0] argument. The chip will transmit all of the
contents of the FIFO and the ipksent interrupt will occur. When this event occurs, the chip will return to the READY
state as defined by TXCOMPLETE_STATE[3:0] = 30h.
4.2.2. Direct Mode
For legacy systems that perform packet handling within the host MCU or other baseband chip, it may not be desirable to
use the FIFO. For this scenario, a Direct Mode is provided which bypasses the FIFOs entirely. In TX direct mode, the TX
modulation data is applied to an input pin of the chip and processed in "real time" (i.e., not stored in a register for
transmission at a later time). Any of the GPIO may be configured for use as the TX Data input function. Furthermore, an
additional pin may be required for a TX Clock output function if GFSK modulation is desired (only the TX Data input pin
is required for FSK). To achieve direct mode the GPIO must be configured in “GPIO_PIN_CFG” API command as well as
the “MODEM_MOD_TYPE” API property. For GFSK “TX_DIRECT_MODE_TYPE” must be set to synchronous. For
ASK or FSK direct mode type should be set to asynchronous. The MOD_SOURCE[1:0] should be set to 01h for are all
direct mode configurations. In RX direct mode, the RX Data and RX Clock can be programmed for direct (real-time)
output to GPIO pins. The microcontroller may then process the RX data without using the FIFO or packet handler
functions of the RFIC. In RX direct mode, the chip must still acquire bit timing during the Preamble, and thus the
preamble detection threshold must still be programmed. Once the preamble is detected, certain bit timing functions within
the RX Modem change their operation for optimized performance over the remainder of the packet. It is not required that
a Sync word be present in the packet in RX Direct mode; however, if the Sync word is absent then the skipsyn bit must be
set, or else the bit timing and tracking function within the RX Modem will not be configured for optimum performance.
4.2.3. RAW Direct Mode
The only difference between RAW Direct Mode and Direct Mode is the structure of the packet being used. In a
conventional packet structure there is a 101010 preamble pattern which the internal modem uses to perform such
functions as clock recovery. Many legacy applications do not have a 101010 preamble pattern so a special
demodulator has been designed into the Si446x family to handle these types of application scenarios. The RAW
mode demodulator will result in slightly less performance than the standard demodulator with a conventional
preamble pattern but it will still provide glitch-less, stable, low jitter data. To achieve RAW mode the device should
be configured as described in “4.2.2. Direct Mode” and also the RAW mode options should be selected in the
calculator API.
24
Tel: [phone] Fax: [phone] E-mail: [e-mail] http:/ / www.hoperf.com