RFM24W Datasheet, PDF (21/34 Pages) List of Unclassifed Manufacturers – ISM Transceiver module

RFM24W
3.5. Interrupts
The RFM24W is capable of generating an interrupt signal when certain events occur. The chip notifies
the microcontroller that an interrupt event has occurred by setting the nIRQ output pin LOW = 0. This interrupt
signal will be generated when any one (or more) of the interrupt events (corresponding to the Interrupt Status bits)
occur. The nIRQ pin will remain low until the microcontroller reads the Interrupt Status Registers. The nIRQ output
signal will then be reset until the next change in status is detected.
The interrupts sources are grouped into three groups: Packet Handler, Chip Status, and Modem. The individual
interrupts in these groups can be enabled/disabled in the interrupt property registers, 0101, 0102, and 0103. An
interrupt must be enabled for it to trigger an event on the nIRQ pin. The interrupt group must be enabled as well as
the individual interrupts in API property 0100.
Once an interrupt event occurs and the nIRQ pin is low there are two ways to read and clear the interrupts. All of
the interrupts may be read and cleared in the “Get INT Status” API command. By default all interrupts will be
cleared once read. If only specific interrupts want to be read in the fastest possible method the individual interrupt
groups (Packet Handler, Chip Status, Modem) may be read and cleared by the “Get Modem Status”, “Get PH
(packet handler) Status, and “Get Chip Status” API commands.
The instantaneous status of a specific function maybe read if the specific interrupt is enabled or disabled. The
status results are provided after the interrupts and can be read with the same commands as the interrupts.
The fast response registers can also give information about the interrupt groups but reading the fast response
registers will not clear the interrupt and reset the nIRQ pin.
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