KXCJK-1013 Datasheet, PDF (15/31 Pages) List of Unclassifed Manufacturers – Accelerometer Specifications

± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KXCJK-1013
Rev. 2
Dec-2012
Writing to a KXCJK 8-bit Register
Upon power up, the Master must write to the KXCJK’s control registers to set its operational mode. Therefore,
when writing to a control register on the I²C bus, as shown Sequence 1 on the following page, the following
protocol must be observed: After a start condition, SAD+W transmission, and the KXCJK ACK has been
returned, an 8-bit Register Address (RA) command is transmitted by the Master. This command is telling the
KXCJK to which 8-bit register the Master will be writing the data. Since this is I²C mode, the MSB of the RA
command should always be zero (0). The KXCJK acknowledges the RA and the Master transmits the data to
be stored in the 8-bit register. The KXCJK acknowledges that it has received the data and the Master
transmits a stop condition (P) to end the data transfer. The data sent to the KXCJK is now stored in the
appropriate register. The KXCJK automatically increments the received RA commands and, therefore,
multiple bytes of data can be written to sequential registers after each Slave ACK as shown in Sequence 2 on
the following page.
Reading from a KXCJK 8-bit Register
When reading data from a KXCJK 8-bit register on the I²C bus, as shown in Sequence 3 on the next page, the
following protocol must be observed: The Master first transmits a start condition (S) and the appropriate Slave
Address (SAD) with the LSB set at ‘0’ to write. The KXCJK acknowledges and the Master transmits the 8-bit
RA of the register it wants to read. The KXCJK again acknowledges, and the Master transmits a repeated
start condition (Sr). After the repeated start condition, the Master addresses the KXCJK with a ‘1’ in the LSB
(SAD+R) to read from the previously selected register. The Slave then acknowledges and transmits the data
from the requested register. The Master does not acknowledge (NACK) it received the transmitted data, but
transmits a stop condition to end the data transfer. Note that the KXCJK automatically increments through its
sequential registers, allowing data to be read from multiple registers following a single SAD+R command as
shown below in Sequence 4 on the following page. The 8-bit register data is transmitted using a left-most
format, first bit shifted/clocked out being the MSB bit.
If a receiver cannot transmit or receive another complete byte of data until it has performed some other
function, it can hold SCL low to force the transmitter into a wait state. Data transfer only continues when the
receiver is ready for another byte and releases SCL.
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