KXCJK-1013 Datasheet, PDF (14/31 Pages) List of Unclassifed Manufacturers – Accelerometer Specifications

± 2g / 4g / 8g Tri-axis Digital
Accelerometer Specifications
PART NUMBER:
KXCJK-1013
Rev. 2
Dec-2012
SDA SCL
IO_Vdd
SDA
MCU _SCL
SDA
KXCJK
SCL
ADDR
SDA
KXCJK
SCL
ADDR
I²C Operation
Figure 1. Multiple KXCJK I²C Connection
Transactions on the I²C bus begin after the Master transmits a start condition (S), which is defined as a high-
to-low transition on the data line while the SCL line is held high. The bus is considered busy after this
condition. The next byte of data transmitted after the start condition contains the Slave Address (SAD) in the
seven MSBs (Most Significant Bits), and the LSB (Least Significant Bit) tells whether the Master will be
receiving data ‘1’ from the Slave or transmitting data ‘0’ to the Slave. When a Slave Address is sent, each
device on the bus compares the seven MSBs with its internally stored address. If they match, the device
considers itself addressed by the Master. The KXCJK’s Slave Address is comprised of a programmable part
and a fixed part, which allows for connection of multiple KXCJK's to the same I²C bus. The Slave Address
associated with the KXCJK is 000111X, where the programmable bit, X, is determined by the assignment of
ADDR (pin 7) to GND or IO_Vdd. Figure 1 above shows how two KXCJ9's would be implemented on an I²C
bus.
It is mandatory that receiving devices acknowledge (ACK) each transaction. Therefore, the transmitter must
release the SDA line during this ACK pulse. The receiver then pulls the data line low so that it remains stable
low during the high period of the ACK clock pulse. A receiver that has been addressed, whether it is Master or
Slave, is obliged to generate an ACK after each byte of data has been received. To conclude a transaction,
the Master must transmit a stop condition (P) by transitioning the SDA line from low to high while SCL is high.
The I²C bus is now free.
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