TC5299J Datasheet, PDF (8/32 Pages) List of Unclassifed Manufacturers – FAST ETHERNET PCMCIA LAN CONTROLLER

TC5299J
3.3 Power On Configuration
The TC5299J Controller configures itself after a RST signal is applied. When a Power-On-Reset occurs the
TC5299J controller latches up the values on the configuration pins and uses these to configure the internal registers
and options. Internally these pins contain pull-up resistance. If pins are unconnected they have default logic. The
configuration registers are loaded JMP0 & JMP1 setting when RST goes inactive.
A Power-On-Reset also causes the Controller to load the internal PROM from the EEPROM, which can take up to
3 ms. This occurs after “Config-Regs.” has completed. If EECONFIG is high the configuration data loaded on the
falling edge of RST will be overwritten with data read from the serial EEPROM. Regardless of the level on
EECONFIG the PROM store will always be loaded with data from the serial EEPROM during the time specified
as EELOAD.
Figure 1 shows how the RESET circuitry operates.
VCC
RESET
Regload
EEload
The TC5299J Controller use a 93C56/66 EEPROM, The programmed contents of the EEPROM is shown as
following.
D15
D8 D7
D0
CIS byte n
CIS byte n-1
13H
........
........
12H
........
........
11H
CIS byte 3
CIS byte 2
10H
CIS byte 1
CIS byte 0
0FH
Not Used
Config C
0EH
Config. B
Config. A
:::::
Reserved
Reserved
08H
42H
42H
07H
57H
57H
:::::
Reserved
Reserved
04H
Reserved
Reserved
03H
Reserved
bit [0]: 8-bit enable
bit [7:1]: Reserved
02H E
net Address 5
E
net Address 4
01H E
net Address 3
E
net Address 2
00H E
net Address 1
E
net Address 0
EEPROM Programming Map
-8-
Ver. 0.1
07/04/01