TC5299J Datasheet, PDF (21/32 Pages) List of Unclassifed Manufacturers – FAST ETHERNET PCMCIA LAN CONTROLLER

TC5299J
5.7.5 Receive Configuration Register (RCR)
0CH(Write)
This register determines operation of the TC5299J during reception of a packet and is used to program
what types of packets to accept.
7
6
5
4
3
2
1
0
-
-
MON PRO AM
AB
AR
SEP
Bit
Symbol
Description
D0
SEP
D1
AR
D2
AB
D3
AM
D4
PRO
D5
MON
D6
-
Save Errored Packets
0: Packets with receive errors are rejected.
1: Packets with receive errors are accepted. Receive errors are CRC and Frame
Alignment errors.
Accept Runt Packets
0: Packets with fewer than 64 bytes rejected.
1: Packets with fewer than 64 bytes accepted.
Accept Broadcast
0: Packets with all 1's broadcast destination address rejected.
1: Packets with all 1's broadcast destination address accepted.
Accept Multicast
0: Packets with multicast destination address not checked.
1: Packets with multicast destination address checked.
Promiscuous Physical
0: Physical address of node must match the station address programmed in
PAR0-PAR5. (Physical address checked)
1: All packets with any physical address accepted. (physical address not
checked)
Monitor Mode: Enables the receiver to check addresses and CRC on incoming
packets without buffering to memory. The missed packet Tally counter will be
incremented for each recognized packet.
0: Packets buffered to memory.
1: Packets checked for address match, good CRC and frame Alignment but not
buffered to memory.
Reserved
D7
-
Reserved
Note:
D2 and D3 are ”OR'd” together, i. e., if D2 and D3 are set the TC5299J will accept broadcast and
multicast addresses as well as its own physical address. To establish full promiscuous mode, bits D2, D3
and D4 should be set. In addition the multicast hashing array must be set to all 1's in order to accept all
multicast addresses.
5.7.6 Receive Status Register (RSR)
0CH(Read)
This register records status of the received packet, including information on errors and the type of
address match, either physical or multicast. The contents of this register are written to buffer memory by
the DMA after reception of a good packet. If packets with errors are to be saved the receive status is
written to memory at the head of the erroneous packet if an erroneous packet is received. If packets with
errors are to be rejected the RSR will not be written to memory. The contents will be cleared when the
next packet arrives. CRC errors, frame Alignment errors and missed packets are counted internally by
the TC5299J which relinquishes the Host from reading the RSR in real time to record errors for Network
Management functions. The contents of this register are not specified until after the first reception.
7
6
5
4
3
2
1
0
-21-
Ver. 0.1
07/04/01