TC5299J Datasheet, PDF (13/32 Pages) List of Unclassifed Manufacturers – FAST ETHERNET PCMCIA LAN CONTROLLER

TC5299J
5 Configuration Registers
5.1 Configuration Register A
To prevent any accidental writes of this register it is”hidden” behind a previously unused register. Register 0AH
in the Controller's Page 0 of registers was previously reserved on a read. Now Configuration Register A can be
read at that address and can be written to by following a read to 0AH with a write to 0AH. If any other Controller
register accesses take place between the read and the write then the write to 0AH will access the Remote Byte
Count Register 0.
7
6
5
4
3
2
1
0
XX
FREAD FDUPLEX LNK_CFG FULL_CFG IO16CON MIISEL1 MIISEL0
Name
MIISEL[1:0]
IO16CON
FULL_CFG
LNK_CFG
FDUPLEX
PCMIOALL
FREAD
XX
R/W Description
R/W 10: Default value to active the MII bus.
Other: reserved.
R/W When this bit is set high the Controller generates IO16* after REG* active. If low this
output is generated only on address decode.
R/W The bit is described EXLEDF what the polarity is.
0: Low active/ Hi inactive
1: Hi active/ Low inactive
R/W The bit is described EXLEDL what the polarity is.
0: Low active/ Hi inactive
1: Hi active/ Low inactive
R The Full-Duplex setting bit.
1: Full-duplex mode,
0: Half-duplex mode
EL The bit is indicated the decode-number of SA[9:0].
0: Only decode 5 address-lines, SA[5:0].
1: Full decode 10 address-lines, SA[9:0].
R/W The TC5299J Controller supports 4 words Remote DMA read/write cache. When this
bit is set high, Remote DMA cache control will be enabled.
Reserved
PS. EL: The bit only set on EEPROM loading.
5.2 Configuration Register B
To prevent any accidental writes of his register it is ”hidden” behind a previously unused register. Register 0BH in
the Controller's Page 0 of registers was previously reserved on a read. Now Configuration Register B can be read
at that address and can be written to by following a read to 0BH with a write to 0BH. If any other Controller
register accesses take place between the read and the write then the write to 0BH will access the Remote Byte
Count Register 1.
7
6
5
4
3
2
1
0
XX LINT EXTRMII MIICINT MIICIM LINK LCINT LCIM
Name
LCIM
R/W Description
R/W The interrupt mask bit for link status changed. When set to “1”, the Interrupt will
generate on link status changed.
-13-
Ver. 0.1
07/04/01