TC5299J Datasheet, PDF (23/32 Pages) List of Unclassifed Manufacturers – FAST ETHERNET PCMCIA LAN CONTROLLER

TC5299J
Bit
Symbol
D6
RDCE
D7
-
Description
of the Network Tally counters has been set.
DMA Complete Interrupt Enable: Enables Interrupt when Remote DMA transfer
has been completed.
Reserved
5.7.8 Interrupt Status Register (ISR)
07H(Read/Write)
This register is accessed to determine the cause of an interrupt. Any interrupt can be masked in the
interrupt Mask Register (IMR). Individual interrupt bits are cleared by writing a ”1” into the
corresponding bit of the ISR.
The IRQ signal is active as long as any unmasked signal is set, and will not go low until all unmarked
bits in this register have been cleared. The ISR must be cleared after power up by writing it with all 1's.
7
6
5
4
3
2
1
0
RST RDC CNT OVW TXE RXE PTX PRX
Bit
Symbol
D0
PRX
D1
PTX
D2
RXE
D3
TXE
D4
OVW
D5
CNT
D6
RDC
D7
RST
Description
Packet Received: Indicates packet received with no errors.
Packet Transmitted: Indicates packet transmitted with no errors.
Receive Error: Indicates that a packet was received with one or more of the
following errors:
- CRC Error
- Frame Alignment Error
- FIFO Overrun
- Missed Packet
Transmit Error: Set when packet transmitted with one or more of the following
errors:
- Excessive Collisions
- FIFO Underrun
Over Write Warning: Set when receive buffer ring storage resources have been
exhausted. (Local DMA has reached Boundary Pointer).
Counter Over flow: Set when MSB of one or more of the Network Tally Counters
has been set.
Remote DMA Complete: Set when Remote DMA operation has been completed.
Reset Status: A status indicator with no interrupt generated
- Set when TC5299J enters reset state and is cleared when a start command is
issued
- Set when a Receive Buffer Ring overflows and is cleared when leaves
overflow status. Writing to this bit has no effect and powers up high.
5.8 Network Tally Counter Registers (CNTR)
Three 8-bit counters are provided for monitoring the number of CRC errors, Frame Alignment Errors and missed
packets, The maximum count reached by any counter is 192 (C0H). These registers will be cleared when read by
the CPU. The count is recorded in binary in CT0-CT7 of each Tally Register.
CNTR0: Monitor the number of Frame Alignment error
7
6
5
4
3
2
1
0
CT7 CT6 CT5 CT4
CT3 CT2 CT1 CT0
CNTR1: Monitor the number of CRC error
-23-
Ver. 0.1
07/04/01