TC5299J Datasheet, PDF (10/32 Pages) List of Unclassifed Manufacturers – FAST ETHERNET PCMCIA LAN CONTROLLER

TC5299J
4 I/O and Mapping
4.1 I/O Port Address Mapping
This chip is register-liked with Novell's NE2000. The base I/O address of TC5299J Controller is configured by
Configuration Register (either upon power up or by software writing to this register). At that address the following
structure appears.
Base+00H
Base+0FH
Base+10H
Base+17H
Base+18H
Base+1FH
TC5299J
Core
Registers
Data Transfer Port
Reset Port
The registers within this area are 8 bits wide, but the data transfer port is 16 bits wide. By accessing the data transfer
port (using I/O instructions) the user can transfer data to or from the TC5299J 's internal memory.
4.2 EEPROM/SRAM Memory Mapping
The TC5299J Controller's internal memory map is as shown below.
D15
0000H
001FH
D7
D0
PROM
Reserved
4000H
7FFFH
8K x 16
Buffer RAM
TC5299J Core Memory Map
PROM
Location
00h
01h
02h
03h
04h
05h
06-0Dh
0E,0Fh
10-15h
16-1Dh
1E-1Fh
Location Contents
ETHERNET ADDRESS 0
ETHERNET ADDRESS 1
ETHERNET ADDRESS 2
ETHERNET ADDRESS 3
ETHERNET ADDRESS 4
ETHERNET ADDRESS 5
RESERVED
57h
ETHERNET ADDRESS 0-5
RESERVED
42h
Contents of PROM Map
-10-
Ver. 0.1
07/04/01