TC5299J Datasheet, PDF (19/32 Pages) List of Unclassifed Manufacturers – FAST ETHERNET PCMCIA LAN CONTROLLER

TC5299J
Bit
Symbol
Description
0
1
1
0
1
1
Register Page 1
Register Page 2
Register Page 3
5.7.2 Data Configure register (DCR)
0EH(Write)
This Register is used to program the TC5299J for 8 or 16-bit memory interface, select byte ordering in
16-bit applications and establish FIFO thresholds. The DCR must be initialized prior to loading the
Remote Byte count Registers.
7
6
5
4
3
2
-
FT1 FT0
-
LS
-
1
0
-
WTS
Bit
Symbol
D0
WTS
D1
-
D2
-
D3
LS
D4
-
D5,D6 FT0,FT1
Description
Word Transfer Select
0: Selects byte-wide DMA transfers.
1: Selects word-wide DMA transfers
Note:
When word-wide mode is selected, up to 32k bytes are addressable; A0
remains low.
Reserved
Reserved
Loopback Select
0: Loopback mode selected. Bits D1, D2 of the TCR must also be programmed for
Loopback mode selected.
1: Normal Operation.
Reserved
FIFO Threshold Select: Encoded: FIFO threshold. During reception, the FIFO
threshold indicates the number of bytes (or words) the FIFO has filled serially from
the network before the FIFO is emptied onto memory bus.
RECEIVE THRESHOLDS
FT1 FT0 Word Wide Byte Wide
0 0 2 Word
4 Bytes
0 1 4 Word
8 Bytes
1 0 8 Word
16 Bytes
1 1 12 Word
24 Bytes
During transmission, the FIFO threshold indicates the number of bytes (of words)
the FIFO has filled from the Local DMA before being transferred to the memory.
Thus, the transmission threshold is 16 bytes less the receive threshold.
5.7.3 Transmit configuration Register (TCR)
0DH(Write)
The transmit configuration establishes the actions of the transmitter section of the TC5299J during
transmission of a packet on the network, LB1 and LB0 power up as 0.
7
6
5
4
3
2
1
0
-
-
-
OFST ATD LB1 LB0 CRC
Bit
Symbol
D0
CRC
Description
Inhibit CRC
-19-
Ver. 0.1
07/04/01