HMS87C1808B Datasheet, PDF (73/99 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

HMS87C1X04B/08B/16B
Oscillator
(X_IN pin)
STOP Mode
Internal
Clock
RESET
Internal
RESET
STOP Instruction Execution
Time can not be control by software
Stabilizing Time
t_ST = 64mS @4MHz
Figure 18-3 Timing of STOP Mode Release by RESET
18.2 STOP Mode using Internal RCWDT
In the STOP mode using Internal RC-Oscillated Watchdog Tim-
er, the on-chip oscillator is stopped. But internal RC oscillation
circuit is oscillated in this mode. The on-chip RAM and Control
registers are held. The port pins out the values held by their re-
spective port data register, port direction registers.
The Internal RC-Oscillated Watchdog Timer mode is activat-
ed by setting the bit RCWDT of CKCTLR to “1”. ( This reg-
ister should be written by byte operation. If this register is set
by bit manipulation instruction, for example “set1” or “clr1”
instruction, it may be undesired operation )
Note: After STOP instruction, at least two or more NOP in-
struction should be written
Ex)
LDM WDTR,#1111_1111B
LDM CKCTLR,#0010_1110B
STOP
NOP
NOP
Release the STOP mode using internal RCWDT
The exit from STOP mode using Internal RC-Oscillated Watch-
dog Timer is hardware reset or external interrupt. Reset re-de-
fines all the Control registers but does not change the on-chip
RAM. External interrupts allow both on-chip RAM and Control
registers to retain their values.
If I-flag = 1, the normal interrupt response takes place. In this
case, if the bit WDTON of CKCTLR is set to “0” and the bit
WDTE of IENH is set to “1”, the device will execute the watch-
dog timer interrupt service routine.(Figure 18-4 ) However, if the
bit WDTON of CKCTLR is set to “1”, the device will generate
the internal RESET signal and execute the reset processing. (Fig-
ure 18-5 )
If I-flag = 0, the chip will resume execution starting with the in-
struction following the STOP instruction. It will not vector to in-
terrupt service routine.( refer to Figure 18-1 )
When exit from STOP mode using Internal RC-Oscillated
Watchdog Timer by external interrupt, the oscillation stabiliza-
tion time is required to normal operation. Figure 18-4 shows the
timing diagram. When release the Internal RC-Oscillated Watch-
dog Timer mode, the basic interval timer is activated on wake-up.
It is increased from 00_H until FF_H . The count overflow is set to
start normal operation. Therefore, before STOP instruction, user
must be set its relevant prescaler divide ratio to have long enough
time (more than 20msec). This guarantees that oscillator has
started and stabilized.
By reset, exit from STOP mode using internal RC-Oscillated
Watchdog Timer is shown in Figure 18-5 .
SEP. 2004 Ver 1.03
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