HMS87C1808B Datasheet, PDF (66/99 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

HMS87C1X04B/08B/16B
Example: Register save using push and pop instructions
INTxx: PUSH A
PUSH X
PUSH Y
interrupt processing
POP
Y
POP
X
POP
A
RETI
;SAVE ACC.
;SAVE X REG.
;SAVE Y REG.
;RESTORE Y REG.
;RESTORE X REG.
;RESTORE ACC.
;RETURN
General-purpose register save/restore using push and pop instruc-
tions;
16.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which has
the lowest priority order.
Interrupt vector address of BRK is shared with the vector of
TCALL 0 (Refer to Program Memory Section). When BRK inter-
rupt is generated, B-flag of PSW is set to distinguish BRK from
TCALL 0.
Each processing step is determined by B-flag as shown in Figure
16-4 .
main task
acceptance of
interrupt
interrupt
service task
saving
registers
interrupt return
restoring
registers
BRK or
TCALL0
B-FLAG
=1
BRK
INTERRUPT
ROUTINE
=0
TCALL0
ROUTINE
RETI
RET
16.3 Multi Interrupt
If two requests of different priority levels are received simulta-
neously, the request of higher priority level is serviced. If re-
quests of the interrupt are received at the same time
simultaneously, an internal polling sequence determines by hard-
ware which request is serviced.
Figure 16-4 Execution of BRK/TCALL0
However, multiple processing through software for special fea-
tures is possible. Generally when an interrupt is accepted, the I-
flag is cleared to disable any further interrupt. But as user sets I-
flag in interrupt routine, some further interrupt can be serviced
even if certain interrupt is in progress.
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SEP. 2004 Ver 1.03