HMS87C1808B Datasheet, PDF (70/99 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

HMS87C1X04B/08B/16B
17. WATCHDOG TIMER
The purpose of the watchdog timer is to detect the malfunction
(runaway) of program due to external noise or other causes and
return the operation to the normal condition.
The watchdog timer has two types of clock source.
The first type is an on-chip RC oscillator which does not require
any external components. This RC oscillator is separate from the
external oscillator of the Xin pin. It means that the watchdog tim-
er will run, even if the clock on the Xin pin of the device has been
stopped, for example, by entering the STOP mode.
The other type is a prescaled system clock.
The watchdog timer consists of 7-bit binary counter and the
watchdog timer data register. When the value of 7-bit binary
counter is equal to the lower 7 bits of WDTR, the interrupt re-
quest flag is generated. This can be used as WDT interrupt or re-
set the CPU in accordance with the bit WDTON.
Note: Because the watchdog timer counter is enabled af-
ter clearing Basic Interval Timer, after the bit WDTON set to
“1”, maximum error of timer is depend on prescaler ratio of
Basic Interval Timer.
The 7-bit binary counter is cleared by setting WDTCL(bit7 of
WDTR) and the WDTCL is cleared automatically after 1 ma-
chine cycle.
The RC oscillated watchdog timer is activated by setting the bit
RCWDT as shown below.
:
LDM
LDM
STOP
NOP
NOP
:
CKCTLR,#3FH; enable the RC-osc WDT
WDTR,#0FFH; set the WDT period
; enter the STOP mode
; RC-osc WDT running
The RC oscillation period is vary with temperature, V_DD and
process variations from part to part (approximately, 40~120uS).
The following equation shows the RC oscillated watchdog timer
time-out.
T_RCWDT=CLK_RC×2⁸×[WDTR.6~0]+(CLK_RC×2⁸)/2
where, CLK_RC = 40~120uS
In addition, this watchdog timer can be used as a simple 7-bit tim-
er by interrupt WDTIF. The interval of watchdog timer interrupt
is decided by Basic Interval Timer. Interval equation is as below.
T_WDT = [WDTR.6~0] × Interval of BIT
Clock Control Register
CKCTLR
-
WAKEUP RCWDT WDTON BTCL
-
0
X
1
X
Watchdog Timer Register
BTS2
X
BTS1
X
BTS0
X
WDTR
WDTCL
7-bit Watchdog Counter Register
ADDRESS : ECH
RESET VALUE : -001_0111
Bit Manipulation Not Available
ADDRESS : EDH
RESET VALUE : 0111_1111
Bit Manipulation Not Available
RCWDT
BTS[2:0]
÷8
÷ 16
3
÷ 32
fxin
÷ 64 ⁸
÷ 128
MUX
0
÷ 256
÷ 512
1
÷ 1024
BTCL
Clear
BITR (8-bit)
Internal RC OSC
WDTR (8-bit)
WDTCL WDTON
7-bit Counter
OFD
Overflow Detection
BITIF
Basic Interval Timer
Interrupt
1
CPU RESET
0
Watchdog Timer
Interrupt Request
Figure 17-1 Block Diagram of Watchdog Timer
66
SEP. 2004 Ver 1.03