HMS87C1808B Datasheet, PDF (63/99 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

HMS87C1X04B/08B/16B
16. INTERRUPTS
The HMS87C1X04B/08B/16B interrupt circuits consist of Inter-
rupt enable register (IENH, IENL), Interrupt request flags of
IRQH, IRQL, Interrupt Edge Selection Register (IEDS), priority
circuit and Master enable flag(“I” flag of PSW). The configura-
tion of interrupt circuit is shown in Figure 16-1 and Interrupt pri-
ority is shown in Table 16-1 .
The External Interrupts INT0, INT1, INT2 and INT3 can each be
transition-activated (1-to-0, 0-to-1 and both transition).
The flags that actually generate these interrupts are bit INT0IF,
INT1IF, INT2IF and INT3IF in Register IRQH. When an exter-
nal interrupt is generated, the flag that generated it is cleared by
the hardware when the service routine is vectored to only if the
interrupt was transition-activated.
The Timer 0, Timer 1, Timer 2 and Timer 3 Interrupts are gener-
ated by T0IF, T1IF, T2IF and T3IF, which are set by a match in
their respective timer/counter register. The AD converter Inter-
rupt is generated by ADIF which is set by finishing the analog to
digital conversion. The Watch dog timer Interrupt is generated by
WDTIF which set by a match in Watch dog timer register (when
the bit WDTON is set to “0”). The Basic Interval Timer Interrupt
is generated by BITIF which is set by a overflowing of the Basic
Interval Timer Register(BITR).
Internal bus line
External Int. 0
External Int. 1
IEDS
Timer 0
Timer 1
External Int. 2
External Int. 3
IEDS
Timer 2
Timer 3
IRQH
INT0IF ⁷
INT1IF ⁶
T0IF ⁵
T1IF ⁴
3
INT2IF
INT3IF ²
T2IF ¹
T3IF ⁰
IENH
Interrupt Enable
Register (Higher byte)
A/D Converter
WDT
BIT
SPI
ADIF ⁷
6
WDTIF
5
BITIF
5
SPIF
IRQL
IENL
Interrupt Enable
Register (Lower byte)
I-flag is in PSW, it is cleared by “DI”, set by
“EI” instruction.When it goes interrupt service,
I-flag is cleared by hardware, thus any other
interrupt are inhibited. When interrupt service is
completed by “RETI” instruction, I-flag is set to
“1” by hardware.
Release STOP
I Flag
Interrupt Master
Enable Flag
Interrupt
Vector
Address
Generator
To CPU
Internal bus line
Figure 16-1 Block Diagram of Interrupt Function
SEP. 2004 Ver 1.03
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