HMS87C1808B Datasheet, PDF (47/99 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

HMS87C1X04B/08B/16B
11. Basic Interval Timer
The HMS87C1X04B/08B/16B has one 8-bit Basic Interval Tim-
er that is free-run, can not stop. Block diagram is shown in Figure
11-1 .The 8-bit Basic interval timer register (BITR) is increased
every internal count pulse which is divided by prescaler. Since
prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/
1024 of the oscillator frequency. As the count overflows from
FF_H to 00_H, this overflow causes to generate the Basic interval
timer interrupt. The BITIF is interrupt request flag of Basic inter-
val timer.
When write “1” to bit BTCL of CKCTLR, BITR register is
cleared to “0” and restart to count-up. The bit BTCL becomes “0”
after one machine cycle by hardware.
If the STOP instruction executed after writing “1” to bit WAKE-
UP of CKCTLR, it goes into the wake-up timer mode. In this
mode, all of the block is halted except the oscillator, prescaler
(only fxin÷2048) and Timer0.
If the STOP instruction executed after writing “1” to bit RCWDT
of CKCTLR, it goes into the internal RC oscillated watchdog tim-
er mode. In this mode, all of the block is halted except the internal
RC oscillator, Basic Interval Timer and Watchdog Timer. More
detail informations are explained in Power Saving Function. The
bit WDTON decides Watchdog Timer or the normal 7-bit timer
Note: All control bits of Basic interval timer are in CKCTLR
register which is located at same address of BITR (address
EC_H). Address EC_H is read as BITR, written to CKCTLR.
Therefore, the CKCTLR can not be accessed by bit manip-
ulation instruction.
.
RCWDT
BTS[2:0]
÷8
÷ 16
3
÷ 32
fxin
÷ 64
÷ 128
8
MUX
0
÷ 256
÷ 512
1
÷ 1024
Internal RC OSC
BTCL
Clear
BITR (8BIT)
BITIF
To Watchdog Timer
Basic Interval Timer
Interrupt
Figure 11-1 Block Diagram of Basic Interval Timer
Clock Control Register
CKCTLR
-
WAKEUP RCWDT WDTON BTCL
BTS2
Symbol
WAKEUP
RCWDT
WDTON
BTCL
Function Description
1 : Enables Wake-up Timer
0 : Disables Wake-up Timer
1 : Enables Internal RC Watchdog Timer
0 : Disables Internal RC Watchdog Time
1 : Enables Watchdog Timer
0 : Operates as a 7-bit Timer
1 : BITR is cleared and BTCL becomes “0” automatically
after one machine cycle, and BITR continue to count-up
BTS1 BTS0
ADDRESS : ECH
RESET VALUE : -001_0111
Bit Manipulation Not Available
Basic Interval Timer Clock Selection
000 : fxin ÷ 8
001 : fxin ÷ 16
010 : fxin ÷ 32
011 : fxin ÷ 64
100 : fxin ÷ 128
101 : fxin ÷ 256
110 : fxin ÷ 512
111 : fxin ÷ 1024
Figure 11-2 CKCTLR: Clock Control Register
SEP. 2004 Ver 1.03
43