MC80F0224 Datasheet, PDF (95/128 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

Preliminary
MC80F0208/16/24
processing step is determined by IFR as shown in Figure 19-6.
WDT or WT
Interrupt Request
=0
WDTIF
=1
WDT Interrupt
Routine
Clear WDTIF
=0
WTIF
=1
WDT Interrupt
Routine
Clear WTIF
RETI
UART0(UART1)
Interrupt Request
=0
Tx0IOF(Tx1IOF)
=1
Tx0(Tx1) Interrupt
Routine
Clear Tx0IOF(Tx1IOF)
=0
Rx0IOF(Rx1IOF)
=1
Rx0(Rx1) Interrupt
Routine
Clear Rx0IOF(Rx1IOF)
RETI
Figure 19-6 Software Flowchart of Shared Interrupt Vector
19.4 Multi Interrupt
If two requests of different priority levels are received simulta-
neously, the request of higher priority level is serviced. If re-
quests of the interrupt are received at the same time
simultaneously, an internal polling sequence determines by hard-
ware which request is serviced. However, multiple processing
Main Program
service
TIMER 1
service
enable INT0
disable other
EI
INT0
service
through software for special features is possible. Generally when
an interrupt is accepted, the I-flag is cleared to disable any further
interrupt. But as user sets I-flag in interrupt routine, some further
interrupt can be serviced even if certain interrupt is in progress.
Occur
TIMER1 interrupt
Occur
INT0
In this example, the INT0 interrupt can be serviced without any
pending, even TIMER1 is in progress.
Because of re-setting the interrupt enable registers IENH,IENL
and master enable “EI” in the TIMER1 routine.
enable INT0
enable other
Figure 19-7 Execution of Multi Interrupt
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