MC80F0224 Datasheet, PDF (109/128 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

Preliminary
MC80F0208/16/24
24. POWER FAIL PROCESSOR
The MC80F0208/16/24 has an on-chip power fail detection cir-
cuitry to immunize against power noise. A configuration register,
PFDR, can enable or disable the power fail detect circuitry.
Whenever V_DD falls close to or below power fail voltage for
100ns, the power fail situation may reset or freeze MCU accord-
ing to PFDM bit of PFDR. Refer to “Figure 24-1 Power Fail Volt-
age Detector Register” on page 105.
In the in-circuit emulator, power fail function is not implemented
and user can not experiment with it. Therefore, after final devel-
opment of user program, this function may be experimented or
evaluated.
Note: User can select power fail voltage level according to
PFS0, PFS1 bit of CONFIG register(703FH) at the FLASH
(MC80F0208/16/24) but must select the power fail voltage
level to define PFD option of "Mask Order & Verification
Sheet" at the mask chip(MC80C0208/16/24), because the
power fail voltage level of mask chip (MC80C0208/16/24) is
determined according to mask option.
Note: If power fail voltage is selected to 2.4V or 2.7V on
below 3V operation, MCU is freezed at all the times.
Power Fail Function
Enable/Disable
Level Selection
FLASH
PFDEN flag
PFS0 bit
PFS1 bit
MASK
PFDEN flag
Mask option
Table 24-1 Power fail processor
PFDR
R/W R/W R/W
7
6
5
4
3
2
1
0
-
-
-
-
- PFDEN PFDM PFDS
ADDRESS: 0F7_H
INITIAL VALUE: ---- -000_B
Power Fail Status
0: Normal operate
1: Set to “1” if power fail is detected
PFD Operation Mode
0 : MCU will be frozen by power fail detection
1 : MCU will be reset by power fail detection
* Cautions : Be sure to set bits 3 through 7 to “0”.
PFD Enable Bit
0: Power fail detection disable
1: Power fail detection enable
Figure 24-1 Power Fail Voltage Detector Register
MAR. 2005 Ver 0.2
105