MC80F0224 Datasheet, PDF (83/128 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

Preliminary
MC80F0208/16/24
Asynchronous serial interface status register0 (ASISR)
When a receive error occurs during UART mode, this register in-
dicates the type of error. ASISR can be read by an 8 bit memory
manipulation instruction. The RESET input sets ASISR0 to -----
000B. Figure 17-5 shows the format of ASISR.
.
ASISR0
R
R
R
7
6
5
4
3
2
1
0
-
-
-
- ^{BTC- L} PE0 FE0 OVE0
ADDRESS: 0E7_H
INITIAL VALUE: ---- -000_B
UART0 Parity Error Flag
0: No parity error
1: Parity error (Transmit data parity not matched)
UART0 Frame Error Flag
0: No Frame error
1: Framing error^Note1 (stop bit not detected)
UART0 Overrun Error Flag
0: No overrun error
1: Overrun error^Note2
(Next receive operation was completed before data was read
from receive buffer register (RXR))
Note 1. Even if a stop bit length is set to 2 bits by setting bit2(SL) in
ASIMR, stop bit detection during a recive operation only applies
to a stop bit length of 1bit.
2. Be sure to read the contents of the receive buffer register(RXR)
when an overrun error has occurred.
Until the contents of RXR are read, futher overrun errors will
occur when receiving data.
Figure 17-5 Asynchronous Serial Interface Status Register (ASISR) Format
MAR. 2005 Ver 0.2
79