MC80F0224 Datasheet, PDF (85/128 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

Preliminary
MC80F0208/16/24
17.3 Communication operation
The transmit operation is enabled when bit 7 (TXE0) of the asyn-
chronous serial interface mode register (ASIMR) is set to 1. The
transmit operation is started when transmit data is written to the
transmit shift register (TXR). The timing of the transmit comple-
tion interrupt request is shown in Figure 17-8.
The receive operation is enabled when bit 6 (RXE0) of the asyn-
chronous serial interface mode register (ASIMR) is set to 1, and
input via the RxD pin is sampled. The serial clock specified by
ASIMR is used to sample the RxD pin. Once reception of one
data frame is completed, a receive completion interrupt request
(INT_RX0) occurs. Even if an error has occurred, the receive
data in which the error occurred is still transferred to RXR. When
ASIMR bit 1 (ISRM0) is cleared to 0 upon occurrence of an error,
and INT_RX0 occurs. When ISRM bit is set to 1, INT_RX0 does
not occur in case of error occurrence. Figure 17-8 shows the tim-
ing of the asynchronous serial interface receive completion inter-
rupt request.
In case of using interrupts of UART0 Tx and UART0 Rx togeth-
er, it is necessary to check IFR in interrupt service routine to find
out which interrupt is occurred, because the UART0 Tx and
UART0 Rx is shared with interrupt vector address. These flag
bits must be cleared by software after reading this register.
In case of using interrupts of UART1 Tx and UART1 Rx togeth-
er, it is necessary to check IFR in interrupt service routine to find
out which interrupt is occurred, because the UART1 Tx and
UART1 Rx is shared with interrupt vector address. These flag
bits must be cleared by software after reading this register.
Each processing step is determined by IFR as shown in Figure 17-
7.
UART0(UART1)
Interrupt Request
Tx0IOF(Tx1IOF)
=0
=1
Tx0(Tx1) Interrupt
Routine
Clear Tx0IOF(Tx1IOF)
=0
Rx0IOF(Rx1IOF)
=1
Rx0(Rx1) Interrupt
Routine
Clear Rx0IOF(Rx1IOF)
RETI
Figure 17-7 Shared Interrupt Vector of UART
MAR. 2005 Ver 0.2
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