MC80F0224 Datasheet, PDF (81/128 Pages) List of Unclassifed Manufacturers – 8-BIT SINGLE-CHIP MICROCONTROLLERS

Preliminary
MC80F0208/16/24
ACLK PIN
f_XIN/2 ~ f_XIN/2⁷
MUX
- TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0
(BRGCR)
Internal Data Bus
5-bit counter
match
Decoder
match
5-bit counter
RECEIVE
RxE
1/2
(Divider)
Tx_Clock
1/2
(Divider)
Rx_Clock
TxE
SEND
Figure 17-2 Baud Rate Generator Block Diagram
IFR
-
MSB
R/W R/W R/W R/W R/W R/W
- RX0IOF TX0IOF RX1IOF TX1IOF WTIOF WDTIOF
LSB
ADDRESS: 0DF_H
INITIAL VALUE: --00 0000_B
WDT interrupt occurred flag^NOTE1
WT interrupt occurred flag^NOTE1
UART1 Tx interrupt occurred flag^NOTE2
UART1 Rx interrupt occurred flag^NOTE2
UART0 Tx interrupt occurred flag^NOTE3
UART0 Rx interrupt occurred flag^NOTE3
NOTE1 : _{In case of using interrupts of Watchdog Timer and Watch Timer together, it is}
necessary to check IFR in interrupt service routine to find out which interrupt is
occurred, because the Watchdog timer and Watch timer is shared with interrupt
vector address. These flag bits must be cleared by software after reading this
register.
NOTE2 : _{In case of using interrupts of UART1 Tx and UART1 Rx together, it is necessary}
to check IFR in interrupt service routine to find out which interrupt is occurred,
because the UART1 Tx and UART1 Rx is shared with interrupt vector address.
These flag bits must be cleared by software after reading this register.
NOTE3 : _{In case of using interrupts of UART0 Tx and UART0 Rx together, it is necessary}
to check IFR in interrupt service routine to find out which interrupt is occurred,
because the UART0 Tx and UART0 Rx is shared with interrupt vector address.
These flag bits must be cleared by software after reading this register.
Figure 17-3 IFR : Interrupt Flag Register
MAR. 2005 Ver 0.2
77