NT5DS32M8AT Datasheet, PDF (6/27 Pages) List of Unclassifed Manufacturers – 256Mb DDR333/300 SDRAM

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Block Diagram (64Mb x 4)
CKE
CK
CK
CS
WE
CAS
RAS
Mode
Registers
13
15
13
A0-A12,
BA0, BA1
15
2
2
11 ^{Column-Address}
Counter/Latch
Bank3
Bank1 ^Bank2
CK, CK
DLL
8192
Bank0
Memory
Array
(8192 x 1024 x 8)
Sense Amplifiers
I/O Gating
DM Mask Logic
1024
(x8)
Column
Decoder
10
COL0
1
8
8
8
Data
4
4
4
DQS
Generator
COL0 _Input
Register
Write ^{Mask 1}
1
FIFO
&
1
2
1
Drivers _{8 4}
4
clk
out
clk
in
Data
4
4
1
DQS
1
4
CK,
COL0
CK
1
DQ0-DQ3,
DM
DQS
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
Preliminary
10/01
6
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