NT5DS32M8AT Datasheet, PDF (21/27 Pages) List of Unclassifed Manufacturers – 256Mb DDR333/300 SDRAM

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
AC Input Operating Conditions (0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V, See AC
Characteristics)
Symbol
V_IH(AC)
V_IL(AC)
V_ID(AC)
V_IX(AC)
Parameter/Condition
Input High (Logic 1) Voltage, DQ, DQS, and DM Signals
Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals
Input Differential Voltage, CK and CK Inputs
Input Crossing Point Voltage, CK and CK Inputs
Min
Max
Unit
V_REF + 0.31
V
V_REF − 0.31
V
0.62
V_DDQ + 0.6
V
0.5*V_DDQ − 0.2 0.5*V_DDQ + 0.2 V
Notes
1, 2
1, 2
1, 2, 3
1, 2, 4
1. Input slew rate = 1V/ns.
2. Inputs are not recognized as valid until V_REF stabilizes.
3. V_ID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The value of V_IX is expected to equal 0.5*V_DDQ of the transmitting device and must track variations in the DC level of the same.
I_DD Specifications and Conditions (0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V, See AC
Characteristics)
Symbol
Parameter/Condition
DDR333 DDR333
t_CK=6ns t_CK=6.6ns ^Unit
Operating Current: one bank; active / precharge; t_RC = t_RC (min); DQ, DM, and
I_DD0
DQS inputs changing twice per clock cycle; address and control inputs changing
85
mA
once per clock cycle
Operating Current: one bank; active / read / precharge; Burst = 2; t_RC = t_RC
I_DD1
(min); CL = 2.5; I_OUT = 0mA; address and control inputs changing once per clock
110
mA
cycle
I_DD2P
Precharge Power-Down Standby Current: all banks idle; power-down mode;
CKE ≤ V_IL (max)
15
mA
I_DD2N
Idle Standby Current: CS ≥ V_IH (min); all banks idle; CKE ≥ V_IH (min);
address and control inputs changing once per clock cycle
35
mA
I_DD3P
Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ V_IL (max)
15
mA
Active Standby Current: one bank; active / precharge; CS ≥ V_IH (min);
I_DD3N CKE ≥ V_IH (min); t_RC = t_RAS (max); DQ, DM, and DQS inputs changing twice per
60
mA
clock cycle; address and control inputs changing once per clock cycle
Operating Current: one bank; Burst = 2; reads; continuous burst; address and
I_DD4R
control inputs changing once per clock cycle; DQ and DQS outputs changing
twice per clock cycle; CL = 2.5; I_OUT = 0mA
165
mA
Operating Current: one bank; Burst = 2; writes; continuous burst; address and
I_DD4W control inputs changing once per clock cycle; DQ and DQS inputs changing twice
150
mA
per clock cycle; CL = 2.5
I_DD5
Auto-Refresh Current: t_RC = t_RFC (min)
170
mA
I_DD6
Self-Refresh Current: CKE ≤ 0.2V
3
mA
Operating current: four bank; four bank interleaving with BL = 4, address and
I_DD7
control inputs randomly changing; 50% of data changing at every transfer;
t RC = t RC (min); I OUT = 0mA.
150
mA
Notes
1
1
1
1
1
1
1
1
1
1, 2
1
1. I_DD specifications are tested after the device is properly initialized.
2. Enables on-chip refresh and address counters.
Preliminary
10/01
21
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