NT5DS32M8AT Datasheet, PDF (22/27 Pages) List of Unclassifed Manufacturers – 256Mb DDR333/300 SDRAM

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Electrical Characteristics & AC Timing - Absolute Specifications
(0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5V ± 0.2V; V_DD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)
Symbol
Parameter
t_AC
t_DQSCK
t_CH
t_CL
t_CK
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
Clock cycle time
CL = 2.5
CL = 2.0
DDR333
(-6)
Min
− 0.7
Max
+ 0.7
− 0.7
+ 0.7
0.45
0.55
0.45
0.55
6
12
7.5
12
DDR300
(-66)
Min
− 0.75
Max
+ 0.75
− 0.75
+ 0.75
0.45
0.55
0.45
0.55
6.6
12
7.5
12
t_DH DQ and DM input hold time
0.45
0.5
t_DS DQ and DM input setup time
t_DIPW
t_HZ
t_LZ
t_DQSQ
t_HP
t_QH
t_DQSS
DQ and DM input pulse width (each input)
Data-out high-impedance time from CK/CK
Data-out low-impedance time from CK/CK
DQS-DQ skew (DQS & associated DQ signals)
minimum half clk period for any given cycle;
defined by clk high (t_CH) or clk low (t_CL) time
Data output hold time from DQS
Write command to 1st DQS latching
transition
t_DQSL,H
t_DSS
t_DSH
t_MRD
t_WPRES
t_WPST
t_WPRE
t_IH
DQS input low (high) pulse width (write cycle)
DQS falling edge to CK setup time (write cycle)
DQS falling edge hold time from CK (write cycle)
Mode register set command cycle time
Write preamble setup time
Write postamble
Write preamble
Address and control input hold time
(fast slew rate)
t_IS
Address and control input setup time
(fast slew rate)
t_IH
Address and control input hold time
(slow slew rate)
t_IS
Address and control input setup time
(slow slew rate)
t_IPW
t_RPRE
t_RPST
t_RAS
Input pulse width
Read preamble
Read postamble
Active to Precharge command
0.45
1.75
− 0.7
− 0.7
min
(t_CH,t_CL)
t_HP - t_QHS
0.75
0.35
0.2
0.2
2 x t_CK
0
0.40
0.25
0.75
+ 0.7
+ 0.7
+ 0.4
1.25
0.60
0.5
1.75
− 0.75
− 0.75
min
(t_CH,t_CL)
t_HP - t_QHS
0.75
0.35
0.2
0.2
2 x t_CK
0
0.40
0.25
0.9
+ 0.57
+ 0.75
+ 0.5
1.25
0.60
0.75
0.9
0.8
1.0
0.8
1.0
2.2
2.2
0.9
1.1
0.9
1.1
0.40
0.60
0.40
0.60
42
120,000
45
120,000
Unit Notes
ns
1-4
ns
1-4
t_CK
1-4
t_CK
1-4
ns
1-4
ns
1-4,
15,16
ns
1-4,
15,16
ns
1-4
ns
1-4, 5
ns
1-4, 5
ns
1-4
t_CK
1-4
t_CK
1-4
t_CK
1-4
t_CK
1-4
t_CK
1-4
t_CK
1-4
ns
1-4
ns
1-4, 7
t_CK
1-4, 6
t_CK
1-4
ns
2-4,
9,11,12
ns
2-4,
9,11,12
ns
2-4, 10,
11,12,14
ns
2-4, 10,
11,12,14
ns 2-4, 12
t_CK
1-4
t_CK
1-4
ns
1-4
Preliminary
10/01
22
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