NT5DS32M8AT Datasheet, PDF (4/27 Pages) List of Unclassifed Manufacturers – 256Mb DDR333/300 SDRAM

NT5DS64M4AT NT5DS64M4AW
NT5DS32M8AT NT5DS32M8AW
256Mb DDR333/300 SDRAM
Input/Output Functional Description
Symbol
CK, CK
CKE, CKE0, CKE1
CS, CS0, CS1
RAS, CAS, WE
DM
BA0, BA1
A0 - A12
DQ
DQS
NC
NU
V_DDQ
V_SSQ
V_DD
V_SS
V_REF
Type
Input
Input
Input
Input
Input
Input
Input
Input/Output
Input/Output
Supply
Supply
Supply
Supply
Supply
Function
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during self refresh. The standard pinout includes one CKE pin. Optional pinouts might
include CKE1 on a different pin, in addition to CKE0, to facilitate independent power down control
of stacked devices.
Chip Select: All commands are masked when CS is registered high. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code. The
standard pinout includes one CS pin. Optional pinouts might include CS1 on a different pin, in
addition to CS0, to allow upper or lower deck selection on stacked devices.
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading. Dur-
ing a Read, DM can be driven high, low, or floated.
Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. BA0 and BA1 also determines if the mode register or extended mode
register is to be accessed during a MRS or EMRS cycle.
Address Inputs: Provide the row address for Active commands, and the column address and
Auto Precharge bit for Read/Write commands, to select one location out of the memory array in
the respective bank. A10 is sampled during a Precharge command to determine whether the Pre-
charge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged,
the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode
Register Set command.
Data Input/Output: Data bus.
Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered
in write data. Used to capture write data.
No Connect: No internal electrical connection is present.
Electrical connection is present. Should not be connected at second level of assembly.
DQ Power Supply: 2.5V ± 0.2V.
DQ Ground
Power Supply: 2.5V ± 0.2V.
Ground
SSTL_2 reference voltage: (V_DDQ / 2) ± 1%.
Preliminary
10/01
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