SDA9489X Datasheet, PDF (54/102 Pages) List of Unclassifed Manufacturers – PIP IV Advanced SOPHISTICUS High-End Picture-In-Picture ICs

SDA 9489X
SDA 9589X
Preliminary Data Sheet
I2C Bus
DISPMOD
D6 D5
0
0
0
1
1
0
1
1
Display Mode
selects display modes with equal pictures
single PiP mode
3 x1/9 PiP (same content)
4 x1/16 PiP (same content)
(reserved)
CLPDEL
Clamping Delay
D4 D3 D2 D1 D0 delay of the clamping pulse for the external RGB/YUV
inputs in steps of 8 parent clock periods
0 0 0 0 0 no delay (0)
...
1 1 1 1 1 maximum delay, 256 clock periods of parent
frequency
Subaddress 0Ah
AGCRES
D7
0
1
Automatic Gain Control Reset
resets AGC
normal operation
reset of AGC
AGCMD
D6 D5
0
0
0
1
1
0
1
1
AGC Mode
controls the AGC operation
evaluation of sync height and ADC overflow
evaluation of sync height only
evaluation of ADC overflow only
AGC fixed (gain depends on AGCVAL)
Micronas
6-54