SDA9489X Datasheet, PDF (24/102 Pages) List of Unclassifed Manufacturers – PIP IV Advanced SOPHISTICUS High-End Picture-In-Picture ICs

SDA 9489X
SDA 9589X
Preliminary Data Sheet
System Description
HSP
VSP
VSPDEL
VSPDEL_max=151 (75) ←s
VSPD
(internal)
field 0 window
field 1 window
tH/2 = 32 (16) ←s
tH = 64 (32) ←s
values in brackets () apply for 100Hz systems
Figure 4-8 Field detection and phase adjustment of vertical pulse (VSP)
Depending on the phase between inset and parent signals a correction of the display
raster for the read out data is performed. As the external VSP and HSP signals may
come from different devices with different delay paths, the phase between V-sync and
H-sync is adjustable (VSPDEL). An incorrect setting of VSPDEL may result in wrong or
unreliable field detection of parent channel.
Normally a noise reduction of the incoming parent vertical pulse is performed. With this
function missing vertical pulses are compensated. The circuit works for 50/60 Hz
applications as well as progressive and 100/120Hz application. (S)VGA signals are
supposed to be very stable and therefore not supported by the noise suppression. By
means of VSPNSRQ, vertical noise suppression is switched off.
A great variety of combinations of inset and parent frequencies are possible. The
following table shows some constellations.
Micronas
4-24