SDA9489X Datasheet, PDF (51/102 Pages) List of Unclassifed Manufacturers – PIP IV Advanced SOPHISTICUS High-End Picture-In-Picture ICs

SDA 9489X
SDA 9589X
Preliminary Data Sheet
I2C Bus
Subaddress 06h
HSPINV
D7
0
1
Horizontal Sync Pulse Inversion
inverts the polarity of HSP
no inversion, raising edge is sync reference
HSP inverted, falling edge is sync reference
VSPINV
D6
0
1
Vertical Sync Pulse Inversion
inverts the polarity of VSP
no inversion, raising edge is sync reference
VSP inverted, falling edge is sync reference
VSPNSRQ
D5
0
1
Vertical Sync Pulse Noise Reduction
activates automatic V insertion that generates vertical sync pulses in
case of missing external VSP
on
off
VSPDEL
Vertical Sync Pulse Delay
D4 D3 D2 D1 D0 delay of the vertical sync pulse Note
in steps of 128 parent clocks
0
0
0
0
0 no delay (0)
delay
...
depends on
HZOOM
1
1
1
1
1 maximum delay, 4096 clocks of
parent frequency
Subaddress 07h
FRSEL
D7
0
1
Frame Select
selects between the normal frame and the shaded frame
normal frame
shaded frame with 3D impression
Micronas
6-51