SDA9489X Datasheet, PDF (37/102 Pages) List of Unclassifed Manufacturers – PIP IV Advanced SOPHISTICUS High-End Picture-In-Picture ICs

SDA 9489X
SDA 9589X
Preliminary Data Sheet
System Description
the clamping and blanking pulse because of the modified clock frequency, but the pulse
length is kept nearly constant.
Parent
Video
HSP
allowed
HSP range
BLANKP
CLAMPP
256 T
a
c
b
d
Figure 4-20 PIP horizontal blanking timing
READD
CLPDEL
D2 D1 D0
0
000
0
111
0
000
0
111
1
000
1
111
1
000
1
111
CLPLEN
D1 D0
00
00
01
01
00
00
01
01
a (←s)
Blanking
Start
-1.5
-11
-1.5
-11.0
-0.8
-5.5
-0.8
-5.5
b (←s)
Blanking
Duration
10.5
10.5
7.9
7.9
5.3
5.3
4
4
c (←s)
Clamping
Start
3
-6.4
2.2
-7.3
1.5
-3.2
1.1
-3.6
d (←s)
Clamping
Duration
5
5
3.8
3.8
2.5
2.5
1.9
1.9
Table 4-21 PIP horizontal blanking timing
4.10.1 Pedestal Level Adjustment
The pedestal level adjustment controlled by I²C signals BLKLR, BLKLG, BLKLB
enables the correction of small offset errors, possibly appearing at the successive
blanking stage of RGB processor. This adjustment has an effect on the setup level
during the active line interval of each channel like the brightness adjustment but has an
Micronas
4-37