SDA9489X Datasheet, PDF (23/102 Pages) List of Unclassifed Manufacturers – PIP IV Advanced SOPHISTICUS High-End Picture-In-Picture ICs

SDA 9489X
SDA 9589X
Preliminary Data Sheet
System Description
automatically, if the described restrictions are not fulfilled. Then only every second
incoming field is shown (field mode). Field mode normally shows joint-lines. This is
caused by an update of the memory during read out. The result is that one part of the
picture contains new picture information and the other part contains one earlier written
field. The switching from or to frame mode is free of artifacts.
Activation of frame-mode display is blocked automatically if at least one of the following
conditions is not fulfilled:
• Inset and parent channel have the same field repetition frequency. This means that
frame mode is possible only for 50Hz inset and parent sources or 60Hz inset and
parent sources.
• Interlace signal is detected for inset and parent channel. For progressive scan or
(S)VGA display therefore only field mode is possible. For some VCRs in trick mode,
often no interlace is detected also.
• The number of lines is within a predefined range for inset (FMACTI) or parent
(FMACTP) channel (assuming standard signals according to ITU)
FMACTP
0
1
0
1
parent
standard
50 Hz
50 Hz
60 Hz
60 Hz
number of
lines per field
310...315
290...325
260...265
250...275
FMACTI
0
1
0
1
inset
standard
50 Hz
50 Hz
60 Hz
60 Hz
number of
lines per field
310...315
290...325
260...265
250...275
Table 4-12 Required number of lines for frame mode display
The system may be forced to field mode by means of FIESEL. Either first or second field
is selectable. ’One of both’ takes every second field independent of the field number.
This is meant for sources generating only one field (e.g. video-games).
For progressive scan conversion systems and HDTV / (S)VGA displays a line doubling
mode is available (PROGEN). Every line of the inset picture is read twice.
Memory writing is stopped by FREEZE bit. The field stored in the memory is then
continuously read. As the picture decimation takes place before storing, the picture size
of a frozen picture can not be changed.
Synchronization of memory reading with the parent channel is achieved by processing
the parent horizontal and vertical synchronization signals connected to the pin HSP for
horizontal synchronization and pin VSP for vertical synchronization. HSPINV or VSPINV
respectively allow an inversion of the expected signal polarity.
Micronas
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