TA7S04 Datasheet, PDF (48/198 Pages) List of Unclassifed Manufacturers – Triscend A7S Configurable System-on-Chip Platform

Triscend A7S Configurable System-on-Chip Platform
Table 24. A7S Memory-Mapped Resources.
Allocated
Resource
Space
Base Address
Control Registers (CRU)
64K bytes Fixed
Configuration Memory
256K bytes Fixed
Memory-mapped CSL Functions
1M bytes Relocatable, resizable in FastChip
Scratch Pad
16K bytes Re-locatable with alias at 0
External Flash
16M bytes Fixed with alias at 0
External Dynamic Memory
256M bytes Fixed with alias at 0
Figure 28 illustrates the memory map in two different phases of operation—just after sec-
ondary initialization completes and a more typical normal operating mode, where the
Flash alias is disabled.
The external Flash alias, starting at address 0, can be disabled by the RTOS via the Clear
Reset Memory Map Register. However, before the RTOS disables the Flash, it must
branch to the Flash image at the top of memory. The internal scratchpad SRAM alias is
now available at the bottom of memory. The user application can copy all timing critical
code to the scratchpad RAM including functions such as the interrupt vector table and the
fast interrupt service routine.
For some applications where the Flash must reside at the bottom of memory, the scratch-
pad RAM can be overlaid over the Flash alias at the bottom of memory by changing its
overlay priority.
All the re-mapping control is performed through registers and is explained in the Remap
and Pause Registers section.
A complete memory map, minus any user-created functions, is available in Appendix A.
Memory-Mapped CSL Functions
This region is where CSL functions containing memory-mapped registers are located.
The region is defined in the FastChip address allocation file. By default, the region is 1M
byte in size, starting at address 0x1000_0000, and allocated down toward the bottom of
memory. This region in resizable and relocatable elsewhere in the system memory map.
The default address allocation settings are shown below.
ALLOCATE START=0x1000_0000 SIZE=1M DIRECTION=DOWN;
Cache and Memory Protection Support
The cache, cache controller, and protection unit provide increased system performance as
well as provide basic memory protection capabilities.
The cache controller/protection unit includes eight control registers. The control registers
are normally accessed through the coprocessor interface, using MCR and MRC instructions
to CP15. The processor must be in privileged mode to access these registers.
Cache Description
The cache is an 8Kbyte mixed instruction/data 4-way set associative cache. It holds 2K
words, divided into 512 lines, with 4 words per line. The cache is transparent to software.
The cache is a write-through cache. During write operations, data is always written to its
destination. If the data is present in the cache, then the cache is updated as well. The
CPU interface unit provides a write buffer for increased performance.
SUBJECT TO CHANGE
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