TA7S04 Datasheet, PDF (175/198 Pages) List of Unclassifed Manufacturers – Triscend A7S Configurable System-on-Chip Platform

Pinout Diagrams and Tables
Available Packages and Package Codes
Each Triscend A7S family member is available in different packaging options. The order-
ing code for an A7S device contains a single-character package code that defines the
package style, as shown in Table 60.
Package
Code
Q
G
Table 60. A7S Family Package Options.
Max. Max. Max.
Leads Style Width Length Height
208 PQFP 30.85 30.85 4.07
324 BGA 19.20 19.20 1.80
Units
mm
mm
Footprint-Compatibility
Although the Triscend A7S device family and the Triscend E5 device family share some
common packages, the A7S and E5 families are not pin compatible.
Available PIOs by Package
The number of user-configurable PIO pins depends on the base device type and the
package in which it is packaged. Table 61 shows the available PIOs by package style.
Two values are indicated for each device type, one for a 32-bit data, 24-bit address con-
figuration and one for 8-bit data, 20-bit address—the minimum configuration. In the latter
case, all spare data, address, and control lines are available as user-defined PIO pins.
TA7S04
TA7S20
Table 61. Available PIOs by Package
Package Code Q
G
Leads 208 324
32 Data
24 Address
60
8 Data
20 Address
91
32 Data
24 Address
86 158
8 Data
20 Address
117 189
Package Power Dissipation/Thermal Characteristics
Package Thermal Resistance
Table 62 shows the junction-to-ambient thermal resistance (Θ_JA) for the various A7S pack-
aging options as a function of airflow over the package. Systems without a fan can expect
only minor airflow due to convection in the system. Fans help reduce the thermal resis-
tance by carrying away heat.
Table 62. Thermal Resistance (Theta-JA) for A7S Package Options.
Package
Airflow
Units
Code Leads 0 0.5 1.0 2.0 m/sec
Q
208 28.8 26.9 26.1 24.9 °C/W
G
324 18.0 TBD 16.5 15.3 °C/W
Estimates provided by packaging subcontractor.
TCH305-0001-002
175
SUBJECT TO CHANGE