TA7S04 Datasheet, PDF (121/198 Pages) List of Unclassifed Manufacturers – Triscend A7S Configurable System-on-Chip Platform

The application program resets the watchdog timer by setting the self-clearing
WD_RESET_BIT in the Watchdog Control Register.
Watchdog Registers Memory Map
Address
Base
Offset
+ 0x00
WD_BASE
+ 0x04
+ 0x08
+ 0x0C
Register Name
Watchdog Control
Watchdog Timeout Value
Watchdog Current Value
Watchdog Clear
Access
R/W
R/W
R
W
Watchdog Control Register (WATCHDOG_CONTROL_REG)
Bit
Description/Function
31:1 Reserved
2
Enable Watchdog Reset (EN_WD_RST_BIT):
0: Disable watchdog timer reset
1: Enable watchdog timer reset. A system reset will occur 4096 clock cy-
cles after the Watchdog timer time-out, unless the application program
resets the watchdog timer within the 4096 clock cycle window.
1
Watchdog Reset (WD_RESET_BIT):
0: No effect
1: Reset watchdog timer, including its interrupt flag and reset logic. This
bit is self-clearing.
0
Watchdog Enable (WD_ENABLE_BIT):
0: Disable watchdog timer
1: Enable watchdog timer
System reset value: 0
Watchdog Time-out Value Register (WATCHDOG_TIMEOUT_VAL_REG)
When this register is updated, the counter is also automatically loaded with this register
value.
Bit
Description/Function
31:0 Watchdog Time-out Value
Not reset. Undefined.
Watchdog Current Value Register (WATCHDOG_CURRENT_VAL_REG)
This register is read only.
Bit
Description/Function
31:0 Watchdog Current Value
Not reset. Undefined.
Watchdog Clear Register (WATCHDOG_CLEAR_REG)
This register is used to clear the watchdog interrupt. It is a write-only register.
Bit
Description/Function
31:1 Reserved
0
Clear Watchdog Timer Interrupt (WD_INT_CLR_BIT):
0: No effect.
1: Clear timer interrupt
TCH305-0001-002
121
SUBJECT TO CHANGE