TA7S04 Datasheet, PDF (24/198 Pages) List of Unclassifed Manufacturers – Triscend A7S Configurable System-on-Chip Platform

Triscend A7S Configurable System-on-Chip Platform
Write
Write
Write
Write
Write
Write
Write
Read Read Lower Read
FFFFFFFF 0000xxxx xxxx0000 FFxxxxxx xxFFxxxx xxxxFFxx xxxxxxFF Byte B2 Half-word Word
Bus Clock
WRSEL3
1
2
4
WRSEL2
5
WRSEL1
3
6
WRSEL0
7
RDSEL3
10
RDSEL2
8
RDSEL1
9
RDSEL0
CSI Data Read
00FF0000 0000FFFF FFFFFFFF
CSI Data Write
CSI Address
FFFFFFFF 00000000 00000000 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF
Word
Upper
Half-word
Lower
Half-word
Byte B3 Byte B2 Byte B1 Byte B0 Byte B2
Lower
Half-word
Word
CSL Register
FFFFFFFF 0000FFFF 00000000 FF000000 FFFF0000 FFFFFF00
FFFFFFFF
Figure 12. Idealized data transfers to a 32-bit register shown in Figure 11.
' The CPU writes 0xFF to the upper-most byte, byte B3, of the data register. The CSI
bus automatically duplicates the byte across all four byte lanes, making the CSI Data
Write bus 0xFFFFFFFF. Only a single byte-enable is asserted, controlling the upper 8
bits of the register. The data register captures the data and the register output be-
comes 0xFF000000 on the next clock edge.
( through ) are similar to ' except that different byte-enables are asserted. After ), the
register value becomes 0xFFFFFFFF on the next clock edge.
* The CPU reads from byte B2. Only the RDSEL2 byte-enable is asserted, placing bits
Q[23:16] onto the CSI Data Read bus. All other byte lanes are zero because they are
not selected in this transaction. The value 0x00FF0000 appears on the CSI Data
Read bus.
+ The CPU reads the lower half-word from the data register. The two byte-enables con-
trolling the lower 16 bits of the register place bits Q[15:0] onto the CSI Data Read bus
and the value 0x0000FFFF is captured on the next rising clock edge. All other byte
lanes are zero.
, The CPU reads the entire 32-bit data register as a word-wide transaction. All four
byte-enables are active placing bits Q[31:0] onto the CSI Data Read bus. The
0xFFFFFFFF value is captured on the next rising clock edge.
SUBJECT TO CHANGE
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TCH305-0001-002