TA7S04 Datasheet, PDF (134/198 Pages) List of Unclassifed Manufacturers – Triscend A7S Configurable System-on-Chip Platform

Triscend A7S Configurable System-on-Chip Platform
DMA Controller
The DMA unit is composed of four independent channels. Via program settings, each
channel performs a series of transfers between an I/O device and memory or performs
memory-to-memory transfers. A set of parameters defines the operation of a given trans-
fer including the memory source or destination addresses, the transfer count and a variety
of other transfer characteristics. These parameters are either …
# programmed directly into the corresponding DMA channel control registers by the CPU,
or
# assembled into a series of two-word or four-word descriptors, which operate independ-
ently of the CPU.
DMA Interaction with A7S System
The DMA controller interacts with the other subsystems that comprise the A7S system, as
shown in Figure 65. The DMA interface to each subsystem has been optimized in some
manners, as described below. Each of the four channels operates independently over the
CSI bus.
ARM7TDMI
CPU
CPU Local Bus
DMA Controller
DMA DMA DMA DMA
0
1
2
3
Internal
SRAM
CPU Local
Bus to CSI
Bus Bridge
CSI Bus
Static
Memory
(Flash)
Interface
SDRAM
Interface
Memory-
mapped
Peripheral
I/O Device
Selector
DMA
Control
Register
(Selector)
Configurable System Logic
UART 0
UART 1
Figure 65. The DMA Controller communicates with functions over the CSI bus and
directly with I/O devices implemented in the CSL matrix.
External Memory Interface
There are optional transfer buffers available when the DMA communicates with external
memory. These buffers help maximize system performance. Each DMA channel has op-
tional buffers for transfers to and from SDRAM and Flash, controlled by the
DMA_BUF_EN_FIELD.
SUBJECT TO CHANGE
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TCH305-0001-002