CH7004C Datasheet, PDF (45/51 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder with Macrovision

CHRONTEL
Register Descriptions (continued)
Bit:
Symbol:
Type:
Default:
7
GPIOIN3
R/W
0
6
GPIOIN2
R/W
0
5
GPIOIN1
R/W
0
4
GPIOIN0
R/W
0
3
FSCI19
R/W
0
CH7004C
Address: 1BH
Bits: 8
2
FSCI18
R/W
0
1
FSCI17
R/W
0
0
FSCI16
R/W
0
Bit:
Symbol:
Type:
Default:
7
GOENB3
R/W
1
6
GOENB2
R/W
1
5
GOENB1
R/W
1
4
GOENB0
R/W
1
3
FSCI15
R/W
0
Address: 1CH
Bits: 6
2
FSCI14
R/W
0
1
FSCI13
R/W
0
0
FSCI12
R/W
0
PLL Control Register
Bit:
7
6
Symbol:
Type:
Default:
5
PLLCPI
R/W
0
4
PLLCAP
R/W
0
3
PLLS
R/W
1
Symbol: PLLC
Address: 20H
Bits: 6
2
PLL5VD
R/W
0
1
PLL5VA
R/W
1
0
MEM5V
R/W
0
The following PLL and memory controls are available through the PLL control register:
MEM5V
MEM5V is set to 1 when the memory supply is 5 volts. The default value of 0 is used when the
memory supply is 3.3 volts.
PLL5VA
PLL5VA is set to 1 when the phase-locked loop analog supply is 5 volts (default). A value of 0 is
used when the phase-locked loop analog supply is 3.3 volts.
PLL5VD
PLL5VD is set to 1 when the phase-locked loop digital supply is 5 volts. A value of 0 is used when
the phase-locked loop digital supply is 3.3 volts (default).
PLLS
PLLS controls the number of stages used in the PLL. When the PLL5VA is 1 (5V analog PLL
supply) PLLS should be 1, and seven stages are used. When PLL5VA is 0 (3.3V analog PLL
supply) PLLS should be 0, and five stages are used.
PLLCAP
PLLCAP controls the loop filter capacitor of the PLL. A recommended listing of PLLCAP vs.
Mode is shown below
PLLCPI
PLLCHI controls the charge pump current of the PLL. The default value should be used.
201-0000-024 Rev 2.1, 8/2/99
45