CH7004C Datasheet, PDF (28/51 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder with Macrovision

CHRONTEL
CH7004C
CH7004
CH7004
CH7004
CH7004
CH7004
SD
acknowledge
acknowledge
acknowledge
acknowledge
acknowledge
I²C
SC
1-7
8
9
1-8
9
1-8
9
1-8
9
1-8
9
Start Device ID R/W* ACK RAB ACK Data ACK RAB ACK Data ACK
Stop
Condition
Condition
Note: The acknowledge is from the CH7004 (slave).
Figure 22: Alternating Write Cycles
If AutoInc = 1, then the register address pointer will be incremented automatically and subsequent data bytes will be
written into successive registers without providing an RAB between each data byte. An Auto-increment write cycle
is shown in Figure 23.
CH7004
CH7004
CH7004
CH7004
SD
acknowledge
acknowledge
acknowledge
acknowledge
I²C
SC
1-7
8
9
1-8
9
1-8
9
1-8
9
Start
Device ID R/W* ACK
Condition
RAB _n
ACK
Data _n
ACK
Data _n+1 ACK
Stop
Condition
Note: The acknowledge is from the CH7004 (slave).
Figure 23: Auto-Increment Write Cycle
When the auto-increment mode is enabled (AutoInc is set to 1), the register address pointer continues to increment
for each write cycle until AR[5:0] = 3F (3F is the address of the Address Register). The next byte of information
represents a new auto-sequencing “Starting address,” which is the address of the register to receive the next byte.
The auto-sequencing then resumes based on this new “Starting address.” The auto-increment sequence can be
terminated any time by either a “STOP” or “RESTART” condition. The write operation can be terminated with a
“STOP” condition.
CH7004 Read Cycle Protocols (R/W = 1)
If a master-receiver is involved in a transfer, it must signal the end of data to the slave-transmitter by not generating
an acknowledge on the last byte that was clocked out of the slave. The slave-transmitter CH7004 releases the data
line to allow the master to generate the STOP condition or the RESTART condition.
To read the content of the registers, the master device starts by issuing a “START” condition (or a “RESTART”
condition). The first byte of data, after the START condition, is a DAB with R/W = 0. The second byte is the RAB
with AR[5:0], containing the address of the register that the master device intends to read from in AR[5:0]. The
master device should then issue a “RESTART” condition (“RESTART” = “START,” without a previous “STOP”
condition). The first byte of data, after this RESTART condition, is another DAB with R/W=1, indicating the
master’s intention to read data hereafter. The master then reads the next byte of data (the content of the register
specified in the RAB). If AutoInc = 0, then another RESTART condition, followed by another DAB with R/W = 0
and RAB, is expected from the master device. The master device then issues another RESTART, followed by
another DAB. After that, the master may read another data byte, and so on. In summary, a RESTART condition,
followed by a DAB, must be produced by the master before each of the RAB, and before each of the data read
events. Two consecutive alternating read cycles are shown in Figure 24.
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201-0000-024 Rev 2.1, 8/2/99