CH7004C Datasheet, PDF (36/51 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder with Macrovision

CHRONTEL
CH7004C
Register Descriptions (continued)
Note: For what was formerly defined as the master mode, the user must now externally connect the P-OUT clock to the
XCLK input pin. Although it is possible to set the XCM [1:0] and PCM[1:0] values independent of the input data format,
there are only certain combinations of inpu data format, XCM and PCM, that will result in valid data being demultiplexed
at the input of the device. Refer to the “Input Data Format Register” for these combinations.
Note: Display modes 25 and 26 must use a 2X multiplexed input data format and a 2X XCLK. Display modes 27
and 28 must use a 1X XCLK input data format.
Table 22. Input Data Format Register
XCM[1:0]
PCM[1:0] XCLK
00
00
1X
00
01
1X
00
1X
1X
01
00
2X
01
01
2X
01
1X
2X
1X
00
3X
1X
01
3X
1X
1X
3X
P-OUT
1X
2X
3X
1X
2X
3X
1X
2X
3X
Input Data Modes Supported
0, 1, 2, 3, 4, 5, 7, 8, 9
0, 1, 2, 3, 4, 5, 7, 8, 9
0, 1, 2, 3, 4, 5, 7, 8, 9
2, 4, 5, 7, 8, 9
2, 4, 5, 7, 8, 9
2, 4, 5, 7, 8, 9
6
6
6
The Clock Mode Register also contains the following bits:
• MCP (bit 4) determines which edge of the pixel clock output will be used to latch input data. Zero selects the
negative edge, one selects the positive edge.
• M/S* (bit 6) determines whether the device operates in master or slave clock mode. In master mode (1), the
14.31818MHz clock is used as a frequency reference to the PLL . In slave mode (0) the XCLK input is used
as a reference to the PLL, and is divided by the value specified by XCM[1:0]. The divide by N and M are
forced to one.
• CFRB (bit 7) sets whether the chroma subcarrier free-runs, or is locked to the video signal. One causes the
subcarrier to lock to the TV vertical rate, and should be used when the ACIV bit is set to zero. Zero causes the
subcarrier to free-run, and should be used when the ACIV bit is set to one.
Start Active Video Register
Bit:
Symbol:
Type:
Default:
7
SAV7
R/W
0
6
SAV6
R/W
0
5
SAV5
R/W
0
4
SAV4
R/W
0
3
SAV3
R/W
0
2
SAV2
R/W
0
Symbol: SAV
Address: 07H
Bits: 8
1
SAV1
R/W
0
0
SAV0
R/W
0
This register sets the delay, in pixel increments, from leading edge of horizontal sync to start of active video. The
entire bit field SAV[8:0] is comprised of this register SAV[7:0], plus the MSB value contained in the position
overflow register, bit SAV8. This is decoded as a whole number of pixels, which can be set anywhere between 0 and
511 pixels. Therefore, in any 2X clock mode, the number of 2X clocks from the leading edge of sync to the first
active data must be a multiple of two clocks. In any 3X clock mode, the number of 3X clocks from the leading edge
of sync to the first active data must be a multiple of three clocks.
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201-0000-024 Rev 2.1, 8/2/99