CH7004C Datasheet, PDF (33/51 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder with Macrovision

CHRONTEL
Register Descriptions (continued)
VOS[1:0]
00
Output Format
PAL
01
NTSC
10
PAL-M
CH7004C
11
NTSC-J
Flicker Filter Register
Bit:
7
6
Symbol:
Type:
Default:
Symbol: FFR
Address: 01H
Bits: 6
5
4
3
2
1
0
FC1
FC0
FY1
FY0
FT1
FT0
R/W
R/W
R/W
R/W
R/W
R/W
1
1
0
0
1
0
The flicker filter register provides for adjusting the operation of the various filters used in rendering the on-screen
image. Adjusting settings between minimal and maximal values enables optimization between sharpness and flicker
content. The FC[1:0] bits determine the settings for the chroma channel. The FT[1:0] bits determine the settings for
the text enhancement circuit. The FY[1:0] bits determine the settings for the luma channel. In addition, the Chroma
channel filtering includes a setting to enable the chroma dot crawl reduction circuit.
Note: When writing to register O1H, FY[1:0] is bits 3:2. FT[1:0] is bits 1:0. When reading from the register O1H, FY
[1:0] is bits 1:0 and FT[1:0] is bits 3:2.
Table 18.Flicker Filter Settings
FY[1:0]
00
01
10
11
Settings for Luma Channel
Minimal Flicker Filtering
Slight Flicker Filtering
Maximum Flicker Filtering
Invalid
FT[1:0]
00
01
10
11
Settings for Text Enhancement Circuit
Maximum Text Enhancement
Slight Text Enhancement
Minimum Text Enhancement
Invalid
FC[1:0]
00
01
10
11
Settings for Chroma Channel
Minimal Flicker Filtering
Slight Flicker Filtering
Maximum Flicker Filtering
Enable Chroma DotCrawl Reduction
201-0000-024 Rev 2.1, 8/2/99
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